3.关于谷歌rocket chip生成指令的搜索:
4.一个官方网站,会议记录:
5.会有很多参考资料的列表
备注:ROCC这个有问题,应该是跟当前rocket版本不一致
projiect中可以使用ln软连接。节省内存。
一个关于指令集拓展的用verilig语言写的百度文库的文章:
Extending RISC-V for application-specific requirements: Steve Cox
- Sometimes a pre-defined ISA is insufficient. May require an application-optimised ISA. e.g. the Google TPU
- ASIP designer is a tool for automating ASIP design. The process can start with a pre-existing example model, e..g RISC-V
- ASIP designer has been used in more than 250 unique SoC products
- The speaker gives an example of a header compression accelerator. Start with a simple 3-stage RV32IM core. This is 24.5k gates on TSMC 28HPM at 500MHz and 32GPRs.
- First, consider instruction level parallelism. e.g. switching to a 2-slot VLIW. This reduced cycle could by 21% and increased gate count by 31%.
- Next, try adding application-specific instructions. This reduced the code size by 56%, cycle count by 67%, and added 9% to the gate count (compared to the original baseline).
- Next, try adding a compare immediate and branch instruction. This reduces code size by 8% and cycle count by 18% vs the previous result.