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高清中文版-mips指令基础
IPS (an acronym for Microprocessor without Interlocked Pipeline Stages) is a reduced instruction set computer (RISC) instruction set architecture (ISA)[1]:A-1[2]:19 developed by MIPS Technologies (formerly MIPS Computer Systems).
There are multiple versions of MIPS: including MIPS I, II, III, IV, and V; as well as five releases of MIPS32/64 (for 32- and 64-bit implementations, respectively). As of April 2017, the current version is MIPS32/64 Release 6.[3][4]
MIPS is a load/store architecture (also known as a register-register architecture); except for the load/store instructions used to access memory, all instructions operate on the registers.
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作者:淡泊的猪
来源:CSDN
原文:https://blog.csdn.net/whuzm08/article/details/80437939
版权声明:本文为博主原创文章,转载请附上博文链接!
2018-12-25
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