u-boot_smdkv210 分析三:启动代码lowlevel.s分析

_TEXT_BASE:

 .word TEXT_BASE

 .globl lowlevel_init
lowlevel_init:
 push {lr}                                        1.lr入栈

 /* check reset status  */
 
 ldr r0, =(ELFIN_CLOCK_POWER_BASE+RST_STAT_OFFSET)   2.读取复位标志,如果是睡眠唤醒,跳过接下来的初始化
 ldr r1, [r0]
 bic r1, r1, #0xfff6ffff
 cmp r1, #0x10000
 beq wakeup_reset_pre
 cmp r1, #0x80000
 beq wakeup_reset_from_didle

 /* IO Retention release */
 ldr r0, =(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)   3.复位引脚到默认功能?
 ldr r1, [r0]
 ldr r2, =IO_RET_REL
 orr r1, r1, r2
 str r1, [r0]

 /* Disable Watchdog */
 ldr r0, =ELFIN_WATCHDOG_BASE /* 0xE2700000 */    4.关闭看门狗定时器
 mov r1, #0
 str r1, [r0]

 /* SRAM(2MB) init for SMDKC110 */                   5.配置sram引脚,16位数据宽度,22位地址宽度
 /* GPJ1 SROM_ADDR_16to21 */
 ldr r0, =ELFIN_GPIO_BASE
 
 ldr r1, [r0, #GPJ1CON_OFFSET]
 bic r1, r1, #0xFFFFFF
 ldr r2, =0x444444
 orr r1, r1, r2
 str r1, [r0, #GPJ1CON_OFFSET]

 ldr r1, [r0, #GPJ1PUD_OFFSET]
 ldr r2, =0x3ff
 bic r1, r1, r2
 str r1, [r0, #GPJ1PUD_OFFSET]

 /* GPJ4 SROM_ADDR_16to21 */
 ldr r1, [r0, #GPJ4CON_OFFSET]
 bic r1, r1, #(0xf<<16)
 ldr r2, =(0x4<<16)
 orr r1, r1, r2
 str r1, [r0, #GPJ4CON_OFFSET]

 ldr r1, [r0, #GPJ4PUD_OFFSET]
 ldr r2, =(0x3<<8)
 bic r1, r1, r2
 str r1, [r0, #GPJ4PUD_OFFSET]


 /* CS0 - 16bit sram, enable nBE, Byte base address */
 ldr r0, =ELFIN_SROM_BASE /* 0xE8000000 */
 mov r1, #0x1
 str r1, [r0]

 /* PS_HOLD pin(GPH0_0) set to high */
 ldr r0, =(ELFIN_CLOCK_POWER_BASE + PS_HOLD_CONTROL_OFFSET)
 ldr r1, [r0]
 orr r1, r1, #0x300                                 6.设置PMIC控制引脚
 orr r1, r1, #0x1 
 str r1, [r0]

 /* when we already run in ram, we don't need to relocate U-Boot.
  * and actually, memory controller must be configured before U-Boot
  * is running in ram.
  */
 ldr r0, =0xff000fff                                 7.读取当前PC与链接地址进行比较,如果已经在ram中运行,跳过sdram初始化
 bic r1, pc, r0  /* r0 <- current base addr of code */
 ldr r2, _TEXT_BASE  /* r1 <- original base addr in ram */
 bic r2, r2, r0  /* r0 <- current base addr of code */
 cmp     r1, r2      /* compare r0, r1                  */
 beq     1f   /* r0 == r1 then skip sdram init   */

 /* init PMIC chip */
 bl PMIC_InitIp                                      8.PMIC初始化

 /* init system clock */
 bl system_clock_init                                9.系统时钟初始化

 /* Memory initialize */
 bl mem_ctrl_asm_init                                10.存储器控制器初始化
 
1:
 /* for UART */
 bl uart_asm_init                                    11.串口初始化

 bl tzpc_init                                        12.取消存储保护区域

#if defined(CONFIG_ONENAND)
 bl onenandcon_init                                  13.onenand初始化
#endif

#if defined(CONFIG_NAND)
 /* simple init for NAND */
 bl nand_asm_init                                    14.nand简单的初始化
#endif

 /* check reset status  */
 
 ldr r0, =(ELFIN_CLOCK_POWER_BASE+RST_STAT_OFFSET)
 ldr r1, [r0]
 bic r1, r1, #0xfffeffff
 cmp r1, #0x10000
 beq wakeup_reset_pre                                15.再次检查复位状态?

 /* ABB disable */
 ldr r0, =0xE010C300                                 16.关闭ABB?
 orr r1, r1, #(0x1<<23)
 str r1, [r0]

 /* Print 'K' */
 ldr r0, =ELFIN_UART_CONSOLE_BASE                    17.打印底层初始化完毕字符K
 ldr r1, =0x4b4b4b4b
 str r1, [r0, #UTXH_OFFSET]

 pop {pc}                                            18.返回到start.s

wakeup_reset_from_didle:
 /* Wait when APLL is locked */
 ldr r0, =ELFIN_CLOCK_POWER_BASE                     *深度睡眠需要等待APLL锁定
lockloop:
 ldr r1, [r0, #APLL_CON0_OFFSET]
 and r1, r1, #(1<<29)
 cmp r1, #(1<<29)
 bne  lockloop
 beq exit_wakeup

wakeup_reset_pre:
 mrc p15, 0, r1, c1, c0, 1 @Read CP15 Auxiliary control register
 and r1, r1, #0x80000000 @Check L2RD is disable or not
 cmp r1, #0x80000000  
 bne wakeup_reset  @if L2RD is not disable jump to wakeup_reset *如果L2RD没被禁用,跳转到唤醒复位
 
 bl disable_l2cache                         *禁用l2cache
 bl v7_flush_dcache_all                     *清空dcache
 /* L2 cache enable at sleep.S of kernel
  * bl enable_l2cache
  */

wakeup_reset:
 /* init system clock */
 bl system_clock_init                        *系统时钟初始化
 bl mem_ctrl_asm_init                        *存储器控制初始化
 bl tzpc_init                                *存储器保护禁用
#if defined(CONFIG_ONENAND)
 bl onenandcon_init                          *onenand初始化
#endif
#if defined(CONFIG_NAND)
 bl nand_asm_init                            *nand初始化
#endif

exit_wakeup:
 /*Load return address and jump to kernel*/
 ldr r0, =(INF_REG_BASE+INF_REG0_OFFSET)
 ldr r1, [r0] /* r1 = physical address of s5pc110_cpu_resume function*/

 mov pc, r1  /*Jump to kernel */         *r1存放唤醒的物理地址,返回到内核中
 nop
 nop

/*
 * system_clock_init: Initialize core clock and bus clock.
 * void system_clock_init(void)
 */
system_clock_init:

 ldr r0, =ELFIN_CLOCK_POWER_BASE @0xe0100000

 /* Set Mux to FIN */
 ldr r1, =0x0
 str r1, [r0, #CLK_SRC0_OFFSET]

 ldr r1, =APLL_LOCKTIME_VAL
 str r1, [r0, #APLL_LOCK_OFFSET]

 /* Disable PLL */
#if defined(CONFIG_CHECK_MPLL_LOCK)
retryloop:
#endif
 ldr r1, =0x0
 str r1, [r0, #APLL_CON0_OFFSET]
 ldr r1, =0x0
 str r1, [r0, #MPLL_CON_OFFSET]          *将APLL和MPLL禁用

 ldr r1, =0x0
 str r1, [r0, #MPLL_CON_OFFSET]          *将MPLL禁用

 ldr    r1, [r0, #CLK_DIV0_OFFSET]      *取DIV0值
 ldr r2, =CLK_DIV0_MASK
 bic r1, r1, r2                          *清零

 ldr r2, =CLK_DIV0_VAL
 orr r1, r1, r2
 str r1, [r0, #CLK_DIV0_OFFSET]          *写入DIV0值

 ldr r1, =APLL_VAL
 str r1, [r0, #APLL_CON0_OFFSET]         *分别设置APLL MPLL VPLL

 ldr r1, =MPLL_VAL
 str r1, [r0, #MPLL_CON_OFFSET]

 ldr r1, =VPLL_VAL
 str r1, [r0, #VPLL_CON_OFFSET]
#if defined(CONFIG_EVT1)
 ldr r1, =AFC_ON
 str r1, [r0, #APLL_CON1_OFFSET]         *是否开启AFC
#endif
 mov r1, #0x10000
1: subs r1, r1, #1                      *耗时等待稳定
 bne 1b

#if defined(CONFIG_CHECK_MPLL_LOCK)
 /* MPLL software workaround */
 ldr r1, [r0, #MPLL_CON_OFFSET]
 orr     r1, r1, #(1<<28)                *该位在文档中是保留位?
 str r1, [r0, #MPLL_CON_OFFSET]

 mov r1, #0x100
1: subs r1, r1, #1                      *耗时等待
 bne 1b

 ldr r1, [r0, #MPLL_CON_OFFSET]
 and r1, r1, #(1<<29)
 cmp r1, #(1<<29)
 bne  retryloop                       *未锁定继续重试

 /* H/W lock detect disable */
 ldr r1, [r0, #MPLL_CON_OFFSET]
 bic     r1, r1, #(1<<28)
 str r1, [r0, #MPLL_CON_OFFSET]
#endif

 ldr r1, [r0, #CLK_SRC0_OFFSET]
 ldr r2, =0x10001111
 orr r1, r1, r2
 str r1, [r0, #CLK_SRC0_OFFSET]          *复位时未接入PLL,现在将ACLK等接入PLL

#if defined(CONFIG_MCP_AC)

 /* CLK_SRC6[25:24] -> OneDRAM clock sel = MPLL */
 ldr r1, [r0, #CLK_SRC6_OFFSET]
 bic r1, r1, #(0x3<<24)
 orr r1, r1, #0x01000000
 str r1, [r0, #CLK_SRC6_OFFSET]          *DRAM选择SCLKMPLL

 /* CLK_DIV6[31:28] -> 4=1/5, 3=1/4(166MHZ@667MHz), 2=1/3 */
 ldr r1, [r0, #CLK_DIV6_OFFSET]
 bic r1, r1, #(0xF<<28)
 bic r1, r1, #(0x7<<12) @; ONENAND_RATIO: 0 *SCLK_ONENAND = MOUTFLASH / (ONENAND_RATIO + 1)
 orr r1, r1, #0x30000000                     *SCLK_ONEDRAM = MOUTONEDR / (ONEDRAM_RATIO + 1)
 str r1, [r0, #CLK_DIV6_OFFSET]

#elif defined (CONFIG_MCP_N)
 /* CLK_SRC6[25:24] -> OneDRAM clock sel = 00:SCLKA2M, 01:SCLKMPLL */
 ldr r1, [r0, #CLK_SRC6_OFFSET]
 mov r1, #0x00000000
 str r1, [r0, #CLK_SRC6_OFFSET]

 /* CLK_DIV6[31:28] -> 0=1/1 */
 ldr r1, [r0, #CLK_DIV6_OFFSET]
 mov r1, #0x00000000
 str r1, [r0, #CLK_DIV6_OFFSET]


#elif defined (CONFIG_MCP_H)

 /* CLK_SRC6[25:24] -> OneDRAM clock sel = 00:SCLKA2M, 01:SCLKMPLL */
 ldr r1, [r0, #CLK_SRC6_OFFSET]
 bic r1, r1, #(0x3<<24)
 orr r1, r1, #0x00000000
 str r1, [r0, #CLK_SRC6_OFFSET]

 /* CLK_DIV6[31:28] -> 4=1/5, 3=1/4(166MHZ@667MHz), 2=1/3 */
 ldr r1, [r0, #CLK_DIV6_OFFSET]
 bic r1, r1, #(0xF<<28)
 bic r1, r1, #(0x7<<12) @; ONENAND_RATIO: 0
 orr r1, r1, #0x00000000
 str r1, [r0, #CLK_DIV6_OFFSET] 

#elif defined (CONFIG_MCP_B) || defined (CONFIG_MCP_D)

 /* CLK_SRC6[25:24] -> OneDRAM clock sel = 00:SCLKA2M, 01:SCLKMPLL */
 ldr r1, [r0, #CLK_SRC6_OFFSET]
 bic r1, r1, #(0x3<<24)
 orr r1, r1, #0x01000000
 str r1, [r0, #CLK_SRC6_OFFSET]

 /* CLK_DIV6[31:28] -> 4=1/5, 3=1/4(166MHZ@667MHz), 2=1/3 */
 ldr r1, [r0, #CLK_DIV6_OFFSET]
 bic r1, r1, #(0xF<<28)
 bic r1, r1, #(0x7<<12) @; ONENAND_RATIO: 0
 orr r1, r1, #0x30000000
 str r1, [r0, #CLK_DIV6_OFFSET]

#elif defined (CONFIG_MCP_SINGLE)

 /* CLK_DIV6 */
 ldr r1, [r0, #CLK_DIV6_OFFSET]
 bic r1, r1, #(0x7<<12) @; ONENAND_RATIO: 0     *SCLK_ONENAND = MOUTFLASH / (ONENAND_RATIO + 1)
 str r1, [r0, #CLK_DIV6_OFFSET]                  *SCLK_ONEDRAM = MOUTONEDR / (ONEDRAM_RATIO + 1)

#endif 

 mov pc, lr


/*
 * uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
 * void uart_asm_init(void)
 */
uart_asm_init:

 /* set GPIO(GPA) to enable UART */
 @ GPIO setting for UART
 ldr r0, =ELFIN_GPIO_BASE
 ldr r1, =0x22222222
 str    r1, [r0, #GPA0CON_OFFSET]

 ldr     r1, =0x2222
 str     r1, [r0, #GPA1CON_OFFSET]           *设置GPIO为UART

 // HP V210 use. SMDK not use.
#if defined(CONFIG_VOGUES)
 ldr    r1, =0x100
 str    r1, [r0, #GPC0CON_OFFSET]

 ldr    r1, =0x4
 str    r1, [r0, #GPC0DAT_OFFSET]
#endif

 ldr r0, =ELFIN_UART_CONSOLE_BASE  @0xEC000000
 mov r1, #0x0
 str r1, [r0, #UFCON_OFFSET]
 str r1, [r0, #UMCON_OFFSET]

 mov r1, #0x3
 str r1, [r0, #ULCON_OFFSET]

 ldr r1, =0x3c5
 str r1, [r0, #UCON_OFFSET]              *设置位数等

 ldr r1, =UART_UBRDIV_VAL
 str r1, [r0, #UBRDIV_OFFSET]            *设置波特率

 ldr r1, =UART_UDIVSLOT_VAL
 str r1, [r0, #UDIVSLOT_OFFSET]          *波特率小数校正

 ldr r1, =0x4f4f4f4f
 str r1, [r0, #UTXH_OFFSET]  @'O'    *输出u-boot第一个字符‘O’

 mov pc, lr

/*
 * Nand Interface Init for SMDKC110
 */
nand_asm_init:

 /* Setting GPIO for NAND */
 /* This setting is NAND initialze code at booting time in iROM. */

 ldr r0, =ELFIN_GPIO_BASE
 
 ldr r1, [r0, #MP01CON_OFFSET]
 bic r1, r1, #(0xf<<8)
 orr r1, r1, #(0x3<<8)                   *0011 = NFCSn[0]  设置nand flash的选通引脚
 str r1, [r0, #MP01CON_OFFSET]
 
*00 = Pull-up/ down disabled
*01 = Pull-down enabled
*10 = Pull-up enabled
*11 = Reserved

 ldr r1, [r0, #MP01PUD_OFFSET]
 bic r1, r1, #(0x3<<4)                   *取消上拉下拉
 str r1, [r0, #MP01PUD_OFFSET]

 ldr r1, [r0, #MP03CON_OFFSET]
 bic r1, r1, #0xFFFFFF                   *全部设置为nf的功能,CLE ALE WE RE RnB0~3
 ldr r2, =0x22222222
 orr r1, r1, r2
 str r1, [r0, #MP03CON_OFFSET]

 ldr r1, [r0, #MP03PUD_OFFSET]
 ldr r2, =0x3fff
 bic r1, r1, r2
 str r1, [r0, #MP03PUD_OFFSET]           *取消上拉下拉

 ldr r0, =ELFIN_NAND_BASE

 ldr r1, [r0, #NFCONF_OFFSET]
 ldr r2, =0x777F
 bic r1, r1, r2
 ldr r2, =NFCONF_VAL                     *Duration =  HCLK x TACLS  Duration = HCLK x ( TWRPH0 + 1 ) Duration =  HCLK x ( TWRPH1 + 1 )
 orr r1, r1, r2                                               7                          7                                   7
 str r1, [r0, #NFCONF_OFFSET]            *0 = SLC NAND Flash    1 = 512 Bytes/page     1 = 4 address cycle

 ldr r1, [r0, #NFCONT_OFFSET]
 ldr r2, =0x707C7
 bic r1, r1, r2
 ldr r2, =NFCONT_VAL                     *ECC  LOCK   INTERRUPT 等设置
 orr r1, r1, r2
 str r1, [r0, #NFCONT_OFFSET]

 ldr r1, [r0, #NFCONF_OFFSET]
 orr r1, r1, #0x70
 orr r1, r1, #0x7700
 str     r1, [r0, #NFCONF_OFFSET]        *前面已经设置了7770了啊?

 ldr r1, [r0, #NFCONT_OFFSET]
 orr r1, r1, #0x03
 str     r1, [r0, #NFCONT_OFFSET]        *使能NAND控制器

 mov pc, lr

/*
 * Setting TZPC[TrustZone Protection Controller]
 */
tzpc_init:

 ldr r0, =ELFIN_TZPC0_BASE                   无保护区域
  mov r1, #0x0
  str r1, [r0]
  mov r1, #0xff
  str r1, [r0, #TZPC_DECPROT0SET_OFFSET]      取消保护区域译码
  str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
 str r1, [r0, #TZPC_DECPROT2SET_OFFSET]  

  ldr  r0, =ELFIN_TZPC1_BASE
  str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
  str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
 str r1, [r0, #TZPC_DECPROT2SET_OFFSET]  

  ldr r0, =ELFIN_TZPC2_BASE
  str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
  str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
 str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
 str r1, [r0, #TZPC_DECPROT3SET_OFFSET]

  ldr r0, =ELFIN_TZPC3_BASE
  str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
  str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
 str r1, [r0, #TZPC_DECPROT2SET_OFFSET]  

  mov pc, lr

/*
 * OneNAND Interface Init                       *未使用,不分析
 */
onenandcon_init:

 @; GPIO setting for OneNAND
 ldr r0, =ELFIN_GPIO_BASE @0xE0200000
 ldr r1, [r0, #MP01CON_OFFSET]
 orr r1, r1, #0x00550000
 str r1, [r0, #MP01CON_OFFSET]

 ldr r1, [r0, #MP03CON_OFFSET]
 orr r1, r1, #0x0550
 orr r1, r1, #0x00550000
 str r1, [r0, #MP03CON_OFFSET]

 ldr r1, =0xFFFF
 str r1, [r0, #MP01DRV_SR_OFFSET]
 str r1, [r0, #MP03DRV_SR_OFFSET]
 str r1, [r0, #MP06DRV_SR_OFFSET]
 str r1, [r0, #MP07DRV_SR_OFFSET]

wait_orwb:
 @; Read ONENAND_IF_STATUS
 ldr r0, =ELFIN_ONENANDCON_BASE @; 0xB0600000
 ldr r1, [r0, #ONENAND_IF_STATUS_OFFSET]
 bic r1, r1, #0xFFFFFFFE
 cmp r1, #0x0

 @; ORWB != 0x0
 bne wait_orwb

 @; write new configuration to onenand system configuration1 register
 ldr r1, =0xF006   @; Sync.
 ldr r2, =(ELFIN_ONENAND_BASE+0x1E442) @; 0x1E442(REG_SYS_CONF1)
 strh r1, [r2]

 @; read one dummy halfword
 ldrh r1, [r2]
 ldrh r1, [r2]

 @; write new configuration to ONENAND_IF_CTRL
 ldr r0, =ELFIN_ONENANDCON_BASE @; 0xB0600000
 @;ldr r1, =0x2F006   @; ONENAND_IF_CTRL_REG_VAL (GCE off)
 ldr r1, =0x402F006   @; ONENAND_IF_CTRL_REG_VAL (GCE on)
 str r1, [r0, #ONENAND_IF_CTRL_OFFSET]

 mov pc, lr


#ifdef CONFIG_ENABLE_MMU

 #ifdef CONFIG_MCP_SINGLE
/*
 * MMU Table for SMDKC110
 * 0x0000_0000 -- 0xBFFF_FFFF => Not Allowed
 * 0xB000_0000 -- 0xB7FF_FFFF => A:0xB000_0000 -- 0xB7FF_FFFF
 * 0xC000_0000 -- 0xC7FF_FFFF => A:0x3000_0000 -- 0x37FF_FFFF
 * 0xC800_0000 -- 0xDFFF_FFFF => Not Allowed
 * 0xE000_0000 -- 0xFFFF_FFFF => A:0xE000_0000 -- 0XFFFF_FFFF
 */

 /* form a first-level section entry */
.macro FL_SECTION_ENTRY base,ap,d,c,b   // 定义生成描述符的宏,分别控制基地址/访问权限/域/cache/buffer。使用的是1M的section
 .word (\base << 20) | (\ap << 10) | \
       (\d << 5) | (1<<4) | (\c << 3) | (\b << 2) | (1<<1)
.endm
.section .mmudata, "a"                       // 定义MMU数据段,在lds文件里面用到了,“a”表示这是一个需要鉴权的段
 .align 14                                           // 一级页表必须14位对齐,因为C2的[31:14]为TLB基地址,虚地址的[31:20]为索引表的[13:2]。
 // the following alignment creates the mmu table at address 0x4000.
 .globl mmu_table
mmu_table:
 .set __base,0
 // Access for iRAM
 .rept 0x100
 FL_SECTION_ENTRY __base,3,0,0,0
 .set __base,__base+1
 .endr

 // Not Allowed
 .rept 0x200 - 0x100
 .word 0x00000000
 .endr

 .set __base,0x200                              // __base的值可视为物理地址的高12位
 // should be accessed
 .rept 0x600 - 0x200                           // rept后的值可视为虚拟地址的高12位
 FL_SECTION_ENTRY __base,3,0,1,1
 .set __base,__base+1
 .endr

 .rept 0x800 - 0x600
 .word 0x00000000
 .endr

 .set __base,0x800
 // should be accessed
 .rept 0xb00 - 0x800
 FL_SECTION_ENTRY __base,3,0,0,0
 .set __base,__base+1
 .endr

/* .rept 0xc00 - 0xb00
 .word 0x00000000
 .endr */

 .set __base,0xB00
 .rept 0xc00 - 0xb00
 FL_SECTION_ENTRY __base,3,0,0,0
 .set __base,__base+1
 .endr

 .set __base,0x200
 // 256MB for SDRAM with cacheable
 .rept 0xD00 - 0xC00
 FL_SECTION_ENTRY __base,3,0,1,1         *0xC000_0000映射到0x2000_0000
 .set __base,__base+1
 .endr

 // access is not allowed.
 @.rept 0xD00 - 0xC80
 @.word 0x00000000
 @.endr

 .set __base,0xD00
 // 1:1 mapping for debugging with non-cacheable
 .rept 0x1000 - 0xD00
 FL_SECTION_ENTRY __base,3,0,0,0
 .set __base,__base+1
 .endr 
 
 #else // CONFIG_MCP_AC, CONFIG_MCP_H, CONFIG_MCP_B

/*
 * MMU Table for SMDKC110
 * 0x0000_0000 -- 0xBFFF_FFFF => Not Allowed
 * 0xB000_0000 -- 0xB7FF_FFFF => A:0xB000_0000 -- 0xB7FF_FFFF
 * 0xC000_0000 -- 0xC7FF_FFFF => A:0x3000_0000 -- 0x37FF_FFFF
 * 0xC800_0000 -- 0xDFFF_FFFF => Not Allowed
 * 0xE000_0000 -- 0xFFFF_FFFF => A:0xE000_0000 -- 0XFFFF_FFFF
 */

 /* form a first-level section entry */
.macro FL_SECTION_ENTRY base,ap,d,c,b
 .word (\base << 20) | (\ap << 10) | \
       (\d << 5) | (1<<4) | (\c << 3) | (\b << 2) | (1<<1)
.endm
.section .mmudata, "a"
 .align 14
 // the following alignment creates the mmu table at address 0x4000.
 .globl mmu_table
mmu_table:
 .set __base,0
 // Access for iRAM
 .rept 0x100
 FL_SECTION_ENTRY __base,3,0,0,0
 .set __base,__base+1
 .endr

 // Not Allowed
 .rept 0x300 - 0x100
 .word 0x00000000
 .endr

#if defined(CONFIG_MCP_N)
 .set __base,0x300
 // should be accessed
 .rept 0x400 - 0x300
 FL_SECTION_ENTRY __base,3,0,1,1
 .set __base,__base+1
 .endr
#else
 .set __base,0x300
 // should be accessed
 .rept 0x350 - 0x300
 FL_SECTION_ENTRY __base,3,0,1,1
 .set __base,__base+1
 .endr

 // Not Allowed
 .rept 0x400 - 0x350
 .word 0x00000000
 .endr
#endif

 .set __base,0x400
 // should be accessed
 .rept 0x500 - 0x400
 FL_SECTION_ENTRY __base,3,0,1,1
 .set __base,__base+1
 .endr

 .rept 0x800 - 0x500
 .word 0x00000000
 .endr

 .set __base,0x800
 // should be accessed
 .rept 0xb00 - 0x800
 FL_SECTION_ENTRY __base,3,0,0,0
 .set __base,__base+1
 .endr

 .set __base,0xB00
 .rept 0xc00 - 0xb00
 FL_SECTION_ENTRY __base,3,0,0,0
 .set __base,__base+1
 .endr

#if defined(CONFIG_MCP_N)
 .set __base,0x300
 // 256MB for SDRAM with cacheable
 .rept 0xD00 - 0xC00
 FL_SECTION_ENTRY __base,3,0,1,1
 .set __base,__base+1
 .endr
#else
 .set __base,0x300
 // 80MB for SDRAM with cacheable
 .rept 0xC50 - 0xC00
 FL_SECTION_ENTRY __base,3,0,1,1
 .set __base,__base+1
 .endr

 // Not Allowed
 .rept 0xD00 - 0xC50
 .word 0x00000000
 .endr
#endif

 .set __base,0xD00
 // 1:1 mapping for debugging with non-cacheable
 .rept 0x1000 - 0xD00
 FL_SECTION_ENTRY __base,3,0,0,0
 .set __base,__base+1
 .endr
 #endif
#endif

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