js logic operator

logical expression of js

 

&& ,||, !

 

operand:

the 3 operator all accept any values as operand,

 

return value:

&& and || return one of the 2 operand as return value,

! always return true or false as return value,

 

------

truthy & falsy value

 

falsy value:

false, null, undefined, 0, -0, '', NaN,

 

truthy value:

any other value,

 

------

&&

 

logic:

when left value is falsy, return left value,

when left value is truthy, return right value,

 

short circuit:

if left value is falsy, then the right value will not be evaluated,

 

e.g.

var a=1;

var b=2;

var c=0;

var d=false;

console.log(a && b); // => 2

console.log(a && c); // => 0

console.log(a && d); // => false

console.log(c && b); // => 0

console.log(c && d); // => 0

console.log(d && c); // => false

 

------

||

 

logic:

when left value is truthy, return left value,

when left value is falsy, return right value,

 

short circuit:

if left value is truthy, then the right value will not be evaluated,

 

e.g.

var a=1;

var b=2;

var c=0;

var d=false;

console.log(a || b); // => 1

console.log(a || c); // => 1

console.log(a || d); // => 1

console.log(c || b); // => 2

console.log(c || d); // => false

console.log(d || c); // => 0

 

------

!

 

logic:

if value is truthy, return false,

if value is falsy, return true,

 

e.g.

var a=1;

var b=2;

var c=0;

var d=false;

console.log(!a); // => false

console.log(!b); // => false

console.log(!c); // => true

console.log(!d); // => true

 

------


  • 0
    点赞
  • 0
    收藏
    觉得还不错? 一键收藏
  • 0
    评论
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY QIANGDAQI IS PORT( CLK, CLK2, S0, S1, S2, S3, S4, S5, S6, STOP, RST: IN STD_LOGIC; N, K, Q_OUT: OUT STD_LOGIC; M: OUT STD_LOGIC_VECTOR(1 DOWNTO 0); A, B, C, D, E, F, G: OUT STD_LOGIC ); END QIANGDAQI; ARCHITECTURE BHV OF QIANGDAQI IS COMPONENT QDJB IS PORT( CLK2, RST: IN STD_LOGIC; S0, S1, S2, S3, S4, S5, S6: IN STD_LOGIC; -- Added S6 TMP: OUT STD_LOGIC; STATES: OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ); END COMPONENT; COMPONENT JS IS PORT( CLK, RST, S, STOP: IN STD_LOGIC; WARN: OUT STD_LOGIC; TA, TB: BUFFER STD_LOGIC_VECTOR(5 DOWNTO 0) ); END COMPONENT; COMPONENT SJXZ IS PORT( CLK2, RST: IN STD_LOGIC; S: OUT STD_LOGIC_VECTOR(1 DOWNTO 0); A, B, C: IN STD_LOGIC_VECTOR(3 DOWNTO 0); Y: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END COMPONENT; COMPONENT YMQ IS PORT( AIN4: IN STD_LOGIC_VECTOR(3 DOWNTO 0); DOUT7: OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ); END COMPONENT; COMPONENT ALARM IS PORT( CLK, I: IN STD_LOGIC; Q: OUT STD_LOGIC ); END COMPONENT; SIGNAL STATES_OUT, TA_OUT, TB_OUT, Y_OUT: STD_LOGIC_VECTOR(6 DOWNTO 0); SIGNAL LEDOUT: STD_LOGIC_VECTOR(6 DOWNTO 0); SIGNAL W: STD_LOGIC; BEGIN A <= LEDOUT(6); B <= LEDOUT(5); C <= LEDOUT(4); D <= LEDOUT(3); E <= LEDOUT(2); F <= LEDOUT(1); G <= LEDOUT(0); U1: QDJB PORT MAP(CLK2, RST, S0, S1, S2, S3, S4, S5, S6, TMP => K, STATES => STATES_OUT); U2: JS PORT MAP(CLK, RST, S0 & S1 & S2 & S3 & S4 & S5, STOP, WARN => N, TA => TA_OUT, TB => TB_OUT); -- Combined S0 to S5 U3: SJXZ PORT MAP(CLK2 => CLK2, RST => RST, S => M, A => STATES_OUT, B => TA_OUT, C => TB_OUT, Y => Y_OUT); U4: YMQ PORT MAP(AIN4 => Y_OUT, DOUT7 => LEDOUT); U5: ALARM PORT MAP(CLK2, STOP, Q_OUT); -- Replaced S with STError (10327): VHDL error at qiangdaqi.vhd(69): can't determine definition of operator ""&"" -- found 0 possible definitionsOP END BHV;
06-10
评论
添加红包

请填写红包祝福语或标题

红包个数最小为10个

红包金额最低5元

当前余额3.43前往充值 >
需支付:10.00
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明:

1.余额是钱包充值的虚拟货币,按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载,可以购买VIP、付费专栏及课程。

余额充值