-- Quartus II VHDL Template
-- Basic Shift Register
library ieee;
use ieee.std_logic_1164.all;
entity simpleDome is
port
(
a,b,c,d : in std_logic;
x,y,z : out std_logic
);
end entity;
architecture rtl of simpleDome is
begin
x <= c or d;
y <= a and b;
z <= a or b;
end rtl;
My First Quartus II VHDL Template
最新推荐文章于 2022-06-17 18:54:42 发布