重庆大学数字逻辑实验第三次——存储器

只贴出FIFO代码和约束

我写的优化版本就不贴了

module FIFO2
// #(parameter DATA_WIDTH =8 ,DEPTH=16,NUM=4)
(
    clk,
    data_in,
    write_en,
    read_en,
    rst,
    data_out,
    is_empty,
    is_full
    );
    input clk;//时钟信号
    input [7:0] data_in;//输入数据
    input write_en;//使能写
    input read_en;//使能读
    input rst;//重置信号
    output reg [7:0]data_out ;//输出数据
    output is_empty;//判断空
    output is_full;//判断满
    reg [3:0]cnt=0 ;//计数变量，即队列中的数据量
    reg [7:0] mem[15:0];//储存数据的数组
    reg [3:0] write_ptr=0 ;//读指针
    reg [3:0] read_pre=0;//写指针
    assign is_empty=(cnt==0)?1:0;//判断队列的情况
    assign is_full=(cnt==15)?1:0;
    always @(posedge clk) begin
        if (rst) begin//重置信号
            cnt=0;
            data_out=0;
            write_ptr=0;
            read_pre=0;
        end
        else begin
            if(write_en)begin
                if (!is_full) begin//非满可写
                        mem[write_ptr]=data_in;
                        cnt=cnt+1;
                        write_ptr=(write_ptr+1)%16;
                    end
                else cnt=0;
            end
        end
    end
    //读取
    always @(read_en) begin
        if(read_en)begin
            if(!is_empty)begin
                        data_out=mem[read_pre];
                        cnt=cnt-1;//出队列，-1
                        read_pre=(read_pre+1)%16;//循环使用这一变量
                    end
                    else data_out=8'b0;
        end
    end
endmodule

xdc文件

set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
set_property IOSTANDARD LVCMOS33 [get_ports {data_in[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_in[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_in[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_in[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_in[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_in[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_in[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_in[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_out[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_out[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_out[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_out[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_out[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_out[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_out[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_out[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports is_empty]
set_property IOSTANDARD LVCMOS33 [get_ports is_full]
set_property IOSTANDARD LVCMOS33 [get_ports read_en]
set_property IOSTANDARD LVCMOS33 [get_ports rst]
set_property IOSTANDARD LVCMOS33 [get_ports write_en]
set_property PACKAGE_PIN V17 [get_ports {data_in[0]}]
set_property PACKAGE_PIN V16 [get_ports {data_in[1]}]
set_property PACKAGE_PIN W16 [get_ports {data_in[2]}]
set_property PACKAGE_PIN W17 [get_ports {data_in[3]}]
set_property PACKAGE_PIN W15 [get_ports {data_in[4]}]
set_property PACKAGE_PIN V15 [get_ports {data_in[5]}]
set_property PACKAGE_PIN W14 [get_ports {data_in[6]}]
set_property PACKAGE_PIN W13 [get_ports {data_in[7]}]
set_property PACKAGE_PIN U16 [get_ports {data_out[0]}]
set_property PACKAGE_PIN E19 [get_ports {data_out[1]}]
set_property PACKAGE_PIN U19 [get_ports {data_out[2]}]
set_property PACKAGE_PIN V19 [get_ports {data_out[3]}]
set_property PACKAGE_PIN W18 [get_ports {data_out[4]}]
set_property PACKAGE_PIN U15 [get_ports {data_out[5]}]
set_property PACKAGE_PIN U14 [get_ports {data_out[6]}]
set_property PACKAGE_PIN V14 [get_ports {data_out[7]}]
set_property PACKAGE_PIN R2 [get_ports clk]
set_property PACKAGE_PIN L1 [get_ports is_empty]
set_property PACKAGE_PIN P1 [get_ports is_full]
set_property PACKAGE_PIN T1 [get_ports rst]
set_property PACKAGE_PIN U1 [get_ports read_en]
set_property PACKAGE_PIN W2 [get_ports write_en]

注意使用时，先把write_en/read_en的操作做完再拉时钟