Determine DCI FDRA and CORESET fdResources

NRRG update to R17(2022-12)

(1) DL DCI FDRA calculation

 DCI 1_0 FDRA field:

// update FDRA
riv, err := makeRiv(flags.dldci.fdNumRbs[i], flags.dldci.fdStartRb[i], flags.bwp._bwpNumRbs[INI_DL_BWP])
if err != nil {
    return err
}
flags.dldci._fdRa[i] = fmt.Sprintf("%0*b", flags.dldci._fdBitsRaType1[i], riv)
fmt.Printf("PDSCH(tag=%v): RIV=%v, FDRA bits=%v\n", flags.dldci._tag[i], riv, flags.dldci._fdRa[i])

DCI 1_1 FDRA field:

// update FDRA
riv, err := makeRiv(flags.dldci.fdNumRbs[DCI_11_PDSCH], flags.dldci.fdStartRb[DCI_11_PDSCH], flags.bwp._bwpNumRbs[DED_DL_BWP])
if err != nil {
    return err
}
flags.dldci._fdRa[DCI_11_PDSCH] = fmt.Sprintf("%0*b", flags.dldci._fdBitsRaType1[DCI_11_PDSCH], riv)
fmt.Printf("PDSCH(tag=%v): RIV=%v, FDRA bits=%v\n", flags.dldci._tag[DCI_11_PDSCH], riv, flags.dldci._fdRa[DCI_11_PDSCH])

 (2) UL DCI FDRA calculation:

Note: PUSCH frequency hopping开启时，假定Frequency Hopping Offset字段为“0”或者"00"。

RAR UL Grant:

    // update FDRA
	riv, err := makeRiv(flags.uldci.fdNumRbs[RAR_UL_MSG3], flags.uldci.fdStartRb[RAR_UL_MSG3], flags.bwp._bwpNumRbs[INI_UL_BWP])
	if err != nil {
		return err
	}
	flags.uldci._fdRa[RAR_UL_MSG3] = fmt.Sprintf("%0*b", flags.uldci._fdBitsRaType1[RAR_UL_MSG3], riv)
	fmt.Printf("PUSCH(tag=%v): RIV=%v, FDRA bits=%v\n", flags.uldci._tag[RAR_UL_MSG3], riv, flags.uldci._fdRa[RAR_UL_MSG3])
	if flags.uldci.fdFreqHop[RAR_UL_MSG3] != "disabled" {
		var ulHopBits int
		if flags.bwp._bwpNumRbs[INI_UL_BWP] >= 50 {
			ulHopBits = 2
		} else {
			ulHopBits = 1
		}

		v, _ := strconv.Atoi(flags.uldci._fdRa[RAR_UL_MSG3][:ulHopBits])
		if v != 0 {
			return errors.New(fmt.Sprintf("The first %v bits of RIV must be all zeros when frequency hopping is enabled!", ulHopBits))
		}
	}

DCI 0_1 FDRA:

        // update FDRA
		riv, err := makeRiv(flags.uldci.fdNumRbs[DCI_01_PUSCH], flags.uldci.fdStartRb[DCI_01_PUSCH], flags.bwp._bwpNumRbs[DED_UL_BWP])
		if err != nil {
			return err
		}
		flags.uldci._fdRa[DCI_01_PUSCH] = fmt.Sprintf("%0*b", flags.uldci._fdBitsRaType1[DCI_01_PUSCH], riv)
		fmt.Printf("PUSCH(tag=%v): RIV=%v, FDRA bits=%v\n", flags.uldci._tag[DCI_01_PUSCH], riv, flags.uldci._fdRa[DCI_01_PUSCH])
		if flags.uldci.fdFreqHop[DCI_01_PUSCH] != "disabled" {
			var ulHopBits int
			if flags.bwp._bwpNumRbs[DED_UL_BWP] >= 50 {
				ulHopBits = 2
			} else {
				ulHopBits = 1
			}

			v, _ := strconv.Atoi(flags.uldci._fdRa[DCI_01_PUSCH][:ulHopBits])
			if v != 0 {
				return errors.New(fmt.Sprintf("The first %v bits of RIV must be all zeros when frequency hopping is enabled!", ulHopBits))
			}
		}

（3）CORESET frequencyAllocationResources field:

    if crbStart%6 == 0 && numRbs%6 == 0 {
		fdres := []byte(fmt.Sprintf("%045b", 0))
		// refer to 38.213 vh40
		// 10.1	UE procedure for determining physical downlink control channel assignment
		// ...if a CORESET is not associated with any search space set configured with freqMonitorLocations, the bits of the bitmap have a one-to-one mapping with non-overlapping groups of 6 consecutive PRBs, in ascending order of the PRB index in the DL BWP bandwidth of N_BWP_RB PRBs with starting common RB position N_start_BWP, where the first common RB of the first group of 6 PRBs has common RB index 6*ceil(N_start_BWP/6) if rb-Offset is not provided...
		rb0grp0 := utils.CeilInt(6 * float64(flags.bwp._bwpStartRb[DED_DL_BWP]) / 6)
		bit0 := (crbStart - rb0grp0) / 6
		nbits := numRbs / 6
		for i := 0; i < nbits; i++ {
			fdres[bit0+i] = '1'
		}
		flags.searchspace._coreset1FdRes = string(fdres)
	} else {
		return errors.New(fmt.Sprintf("Both coreset1StartCrb and coreset1NumRbs must be multiples of 6!"))
	}