LLVM Target Description相关代码学习 第一篇 target.td

• HwMode

  class HwMode<string FS> {
    // A string representing subtarget features that turn on this HW mode.
    // For example, "+feat1,-feat2" will indicate that the mode is active
    // when "feat1" is enabled and "feat2" is disabled at the same time.
    // Any other features are not checked.
    // When multiple modes are used, they should be mutually exclusive,
    // otherwise the results are unpredictable.
    string Features = FS;
  }
  

  一个字符串表示自平台的特性，打开HW模式。例如，"+feat1,-feat2" 表示在feat1 开启并且 feat2 关闭时这个模式处于活动状态。其他任何特性都不检查。当使用了多个模式，它们应该互相不包含，否则导致不可预期的结果。

• DefaultMode

  // A special mode recognized by tablegen. This mode is considered active
  // when no other mode is active. For targets that do not use specific hw
  // modes, this is the only mode.
  def DefaultMode : HwMode<"">;

  tablegen识别的一个特殊的模式。没有其他模式处于活动状态时，这个模式被认为是活动的。对于没有使用特定的hw模式的目标，这个是唯一的模式。

• HwModeSelect

• // A class used to associate objects with HW modes. It is only intended to
  // be used as a base class, where the derived class should contain a member
  // "Objects", which is a list of the same length as the list of modes.
  // The n-th element on the Objects list will be associated with the n-th
  // element on the Modes list.
  class HwModeSelect<list<HwMode> Ms> {
    list<HwMode> Modes = Ms;
  }

  用于将一个对象与HW模式关联的类。它仅被用作基类，它的派生类应该包含一个“Objects”，一个模式列表相同长度的表。Objects列表的第n个元素与模式列表中的第n个元素相关联。

• Instruction
   

  //===----------------------------------------------------------------------===//
  // 指令集描述 - 这些类与Target/TargetInstrInfo.h的C++类对应
  //  
  //
  class Instruction {
    string Namespace = "";    //命名空间
  
    dag OutOperandList;       // MI def操作数列表的DAG.
    dag InOperandList;        // 包含MI use操作数列表的DAG.
    string AsmString = "";    // 打印成怎样的汇编码
  
    // Pattern - Set to the DAG pattern for this instruction, if we know of one,
    // otherwise, uninitialized.
    list<dag> Pattern;
  
    // The follow state will eventually be inferred automatically from the
    // instruction pattern.
  
    list<Register> Uses = []; // 默认需要使用的非操作数寄存器
    list<Register> Defs = []; // 默认需要修改的非操作数寄存器
  
    // Predicates - List of predicates which will be turned into isel matching
    // code.
    list<Predicate> Predicates = [];  //谓语列表
  
    // Size - Size of encoded instruction, or zero if the size cannot be determined
    // from the opcode.
    int Size = 0;    //指令的长度，字节为单位
  
    // DecoderNamespace - The "namespace" in which this instruction exists, on
    // targets like ARM which multiple ISA namespaces exist.
    string DecoderNamespace = "";
  
    // Code size, for instruction selection.
    // FIXME: What does this actually mean?
    int CodeSize = 0;    //代码大小
  
    // Added complexity passed onto matching pattern.
    int AddedComplexity  = 0;    
  
    // 这些位获取上层指令的语意信息
    // instruction.
    bit isReturn     = 0;     // 返回指令？
    bit isBranch     = 0;     // 分支/跳转指令?
    bit isEHScopeReturn = 0;  // 结束异常指令作用域?
    bit isIndirectBranch = 0; // 间接分支指令?
    bit isCompare    = 0;     // 比较指令?
    bit isMoveImm    = 0;     // 传送立即数指令?
    bit isMoveReg    = 0;     // 传送寄存器指令?
    bit isBitcast    = 0;     // 位转换指令?
    bit isSelect     = 0;     // 选择指令?
    bit isBarrier    = 0;     // 控制流陷入该指令吗?
    bit isCall       = 0;     // 函数调用指令？
    bit isAdd        = 0;     // 加法指令？
    bit isTrap       = 0;     // 自陷指令?
    bit canFoldAsLoad = 0;    // 可以折叠为简单的内存访问指令吗?
    bit mayLoad      = ?;     // 可能访问内存吗?
    bit mayStore     = ?;     // 可能写内存吗?
    bit isConvertibleToThreeAddress = 0;  // 2址指令能提升为3址指令吗?
    bit isCommutable = 0;     // 操作数可以交换吗?
    bit isTerminator = 0;     // 是基本块的终结的一部分吗?
    bit isReMaterializable = 0; // 指令可以重构吗?
    bit isPredicable = 0;     // 指令支持谓语吗?
    bit hasDelaySlot = 0;     // 指令有延迟槽吗?
    bit usesCustomInserter = 0; // Pseudo instr needing special help.
    bit hasPostISelHook = 0;  // 指令选择后需要钩子吗？
    bit hasCtrlDep   = 0;     // 这是指令的 r/w 控制流链吗?
    bit isNotDuplicable = 0;  // 复制指令是否安全?
    bit isConvergent = 0;     // Is this instruction convergent?
    bit isAsCheapAsAMove = 0; // 与传送指令一样消耗吗？
    bit hasExtraSrcRegAllocReq = 0; // 源需要额外的寄存器分配吗?
    bit hasExtraDefRegAllocReq = 0; // Defs 有额外的寄存器分配请求吗?
    bit isRegSequence = 0;    // Is this instruction a kind of reg sequence?
                              // If so, make sure to override
                              // TargetInstrInfo::getRegSequenceLikeInputs.
    bit isPseudo     = 0;     // 这是一条伪指令吗?
                              // 如果是不会编码
                              
    bit isExtractSubreg = 0;  // Is this instruction a kind of extract subreg?
                               // If so, make sure to override
                               // TargetInstrInfo::getExtractSubregLikeInputs.
    bit isInsertSubreg = 0;   // Is this instruction a kind of insert subreg?
                              // If so, make sure to override
                              // TargetInstrInfo::getInsertSubregLikeInputs.
    bit variadicOpsAreDefs = 0; // Are variadic operands definitions?
  
    // Does the instruction have side effects that are not captured by any
    // operands of the instruction or other flags?
    bit hasSideEffects = ?;
  
    // Is this instruction a "real" instruction (with a distinct machine
    // encoding), or is it a pseudo instruction used for codegen modeling
    // purposes.
    // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
    // instructions can (and often do) still have encoding information
    // associated with them. Once we've migrated all of them over to true
    // pseudo-instructions that are lowered to real instructions prior to
    // the printer/emitter, we can remove this attribute and just use isPseudo.
    //
    // The intended use is:
    // isPseudo: Does not have encoding information and should be expanded,
    //   at the latest, during lowering to MCInst.
    //
    // isCodeGenOnly: Does have encoding information and can go through to the
    //   CodeEmitter unchanged, but duplicates a canonical instruction
    //   definition's encoding and should be ignored when constructing the
    //   assembler match tables.
    bit isCodeGenOnly = 0;
  
    // Is this instruction a pseudo instruction for use by the assembler parser.
    bit isAsmParserOnly = 0;
  
    // This instruction is not expected to be queried for scheduling latencies
    // and therefore needs no scheduling information even for a complete
    // scheduling model.
    bit hasNoSchedulingInfo = 0;
  
    InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
  
    // Scheduling information from TargetSchedule.td.
    list<SchedReadWrite> SchedRW;
  
    string Constraints = "";  // OperandConstraint, e.g. $src = $dst.
  
    /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
    /// be encoded into the output machineinstr.
    string DisableEncoding = "";
  
    string PostEncoderMethod = "";
    string DecoderMethod = "";
  
    // Is the instruction decoder method able to completely determine if the
    // given instruction is valid or not. If the TableGen definition of the
    // instruction specifies bitpattern A??B where A and B are static bits, the
    // hasCompleteDecoder flag says whether the decoder method fully handles the
    // ?? space, i.e. if it is a final arbiter for the instruction validity.
    // If not then the decoder attempts to continue decoding when the decoder
    // method fails.
    //
    // This allows to handle situations where the encoding is not fully
    // orthogonal. Example:
    // * InstA with bitpattern 0b0000????,
    // * InstB with bitpattern 0b000000?? but the associated decoder method
    //   DecodeInstB() returns Fail when ?? is 0b00 or 0b11.
    //
    // The decoder tries to decode a bitpattern that matches both InstA and
    // InstB bitpatterns first as InstB (because it is the most specific
    // encoding). In the default case (hasCompleteDecoder = 1), when
    // DecodeInstB() returns Fail the bitpattern gets rejected. By setting
    // hasCompleteDecoder = 0 in InstB, the decoder is informed that
    // DecodeInstB() is not able to determine if all possible values of ?? are
    // valid or not. If DecodeInstB() returns Fail the decoder will attempt to
    // decode the bitpattern as InstA too.
    bit hasCompleteDecoder = 1;
  
    /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
    bits<64> TSFlags = 0;
  
    ///@name Assembler Parser Support
    ///@{
  
    string AsmMatchConverter = "";
  
    /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
    /// two-operand matcher inst-alias for a three operand instruction.
    /// For example, the arm instruction "add r3, r3, r5" can be written
    /// as "add r3, r5". The constraint is of the same form as a tied-operand
    /// constraint. For example, "$Rn = $Rd".
    string TwoOperandAliasConstraint = "";
  
    /// Assembler variant name to use for this instruction. If specified then
    /// instruction will be presented only in MatchTable for this variant. If
    /// not specified then assembler variants will be determined based on
    /// AsmString
    string AsmVariantName = "";
  
    ///@}
  
    /// UseNamedOperandTable - If set, the operand indices of this instruction
    /// can be queried via the getNamedOperandIdx() function which is generated
    /// by TableGen.
    bit UseNamedOperandTable = 0;
  
    /// Should FastISel ignore this instruction. For certain ISAs, they have
    /// instructions which map to the same ISD Opcode, value type operands and
    /// instruction selection predicates. FastISel cannot handle such cases, but
    /// SelectionDAG can.
    bit FastISelShouldIgnore = 0;
  }