6410初始化相关描述

I. • coprocessors CP14 and CP15.   II. STOP mode entering sequence is as follows: 1. User software sets PWR_CFG[6:5] as STOP mode 2. User software generates STANDBYWFI signal by MCR instruction (MCR p15, 0, Rd, c7, c0, 4) 3. SYSCON requests bus controller to finish current AHB bus transaction. 4. AHB bus controller sends acknowledge to SYSCON after current bus transaction is completed. 5. SYSCON requests DOMAIN-V to finish current AXI-bus transaction. 6. AXI bus controller sends acknowledge to SYSCON after current bus transaction is completed. 7. SYSCON requests external memory controllers to enter into self-refresh mode, since the contents in the external memory must be preserved during STOP mode. 8. The memory controllers send acknowledges when they are self-refresh mode. 9. SYSCON changes clock source from PLL output to external oscillator if PLL is used. 10. SYSCON disables power-gating circuitries to eliminate leakage current. (only applied for DEEP-STOP mode) 11. SYSCON disables PLL operations and crystal oscillator.   III. SLEEP mode entering sequence is as follows: 1. User software sets PWR_CFG[6:5] as SLEEP mode 2. User software generates STANDBYWFI signal by MCR instruction (MCR p15, 0, Rd, c7, c0, 4) 3. SYSCON requests bus controller to finish current AHB bus transaction 4. AHB bus controller sends acknowledge to SYSCON after current bus transaction is completed. 5. SYSCON requests DOMAIN-V to finish current AXI-bus transaction. 6. AXI bus controller sends acknowledge to SYSCON after current bus transaction is completed. 7. SYSCON requests external memory controllers to enter into self-refresh mode, since the contents in the external memory must be preserved during SLEEP mode. 8. The memory controllers send acknowledges when they are self-refresh mode. 9. SYSCON changes clock source from PLL output to external oscillator if PLL is used. 10. SYSCON disables PLL operations and crystal oscillator. 11. Finally, SYSCON disables an external power source for internal logic by asserting XPWRRGTON pin to low state. XPWRRGTON signal controls an external regulator.   IV. Pheripheral is accessed via PERI bus, and its address range is from 0x7000_0000 to 0x7FFF_FFFF. All SFRs can be accessed in this address range. Also, if data is needed to transfer from NFCON or CFCON, those data should be transferred via PERI bus.   34.4.1 MEMORY MAP Register        Address          R/W      Description                                     Reset Value WTCON       0x7E004000   R/W    Watchdog timer control register         0x8021 WTDAT       0x7E004004   R/W    Watchdog timer data register             0x8000 WTCNT       0x7E004008   R/W    Watchdog timer count register           0x8000 WTCLRINT 0x7E00400C   W        Watchdog timer interrupt clear register   12.5 SUMMARY OF VIC REGISTERS • Base address of VIC0 is 0x7120_0000 • Base address of VIC1 is 0x7130_0000 • Address of control register = base address + offset Register 　　　　　　Offset 　　Type　　 Description 　　　　　　　　Reset Value VICxIRQSTATUS 　　0x000 　　R　　 IRQ Status Register 　　　　　　0x00000000 VICxFIQSTATUS 　　0x004 　　R 　　FIQ Status Register 　　　　　　0x00000000 VICxRAWINTR 　　　0x008 　　R　　 Raw Interrupt Status Register 　　0x00000000 VICxINTSELECT 　　0x00C 　　RW 　Interrupt Select Register 　　　　0x00000000 VICxINTENABLE 　　0x010 　　RW 　Interrupt Enable Register 　　　　0x00000000 VICxINTENCLEAR　 0x014 　　W　　 Interrupt Enable Clear Register 　 　　- VICxSOFTINT 　　　0x018 　　RW　 Software Interrupt Register　　　　 0x00000000   10.5.21 MEMORY INTERFACE DRIVE STRENGTH CONTROL REGISTER Register Address R/W Description Reset Value MEM0DRVCON 0x7F0081D0 R/W Memory Port 0 Drive strength Control Register 0x10555551 MEM1DRVCON 0x7F0081D4 R/W Memory Port 1 Drive strength Control Register 0x555555   3.4.2.14 Others control register REGISTER ADDRESS R/W DESCRIPTION RESET VALUE OTHERS 0x7E00_F900 R/W Others control register 0x0000_801E   SYNCMODE 　　 [7]     SYNCMODEREQ to ARM 0: Asynchronous mode, 1: Synchronous mode 　　0   CLK_DIV0 　　0x7E00_F020　　 R/W 　　Set clock divider ratio　　 0x0105_1000