该功能的分析基于Nand Mode:
If the value in BTSEL[1:0] from the BOOTCFG register is 00, the NAND mode executes. The outline of
operations followed in the NAND mode is described in Figure 11-2. The NAND boot mode assumes the
NAND is located on the EM_CE0 interface, whose bus configuration is configure by the pins AECFG[3:0].
The pins AECFG[3:0] must be configured such that the proper EMIF signals are availabel for the NAND
device.
First, the device ID of the NAND device is read from the device, and then any necessary information (such
as the block and page sizes, etc.) are obtained from the device information table in the RBL. The device
information in the RBL is based on the list of supported NAND devices. Next, the RBL searches for the
UBL descriptor in page 0 of the block after CIS/IDI block (block 1).
If a valid UBL is not found here, as determined by reading a valid UBL magic number, the next block is
searched. Searching continues for up to 24 blocks. This provision for additional searching is made in case
the first few consecutive blocks have been marked as bad (i.e., they have errors). Searching 24 blocks is
sufficient to handle the errors found in virtually all NAND devices.
When a valid UBL signature is found, the corresponding block number (from 1 to 24) is written to the last
32 bits of ARM internal memory (0x7ffc-0x8000). This feature is provided as a basic debug mechanism.
By reading these 32 bits of memory, via JTAG for example, you can determine in which block the RBL
found a valid UBL signature. If no valid UBL signature is found after searching 24 blocks, the RBL will try
to boot via MMC/SD.
If a valid UBL is found, the UBL descriptor is read and processed. The descriptor gives the information
required for loading and control transfer to the UBL. The UBL is then read and processed. The RBL may
enable any combination of faster EMIF and I-Cache operations based on information in the UBL descriptor
first. Additionally, the descriptor provides information on whether or not DMA should be used during UBL
copying. Once the user-specified start-up conditions are set, the RBL copies the UBL into ARM internal
RAM, starting at address 0x0000: 0020.
Note: The actual copying is performed on the lower 30KB of the TCM data area: 0x10020 -
0x1781F.
The NAND RBL uses the hardware 4-bit ECC to determine if a read error occurs while reading the UBL
into ARM IRAM. If a 4-bit ECC read error is detected, the UBL will correct the error via the ECC correction
algorithm. If the read fails for any other reason, the copy will immediately halt for that instance on magic
number and then the RBL will continue to search the next block following the block in which the magic
number was found for another instance of a magic number. When another magic number is found, the
process is repeated. Using this retry process, the magic number and UBL can be duplicated up to 24
times, giving significant redundancy and error resilience to NAND read errors.
void DM355EvmInit()
{
// Mask all interrupts
AINTC->INTCTL = 0x4;
AINTC->EABASE = 0x0;
AINTC->EINT0 = 0x0;
AINTC->EINT1 = 0x0;
AINTC->FIQ0 = 0xffffffff;
AINTC->FIQ1 = 0xffffffff;
AINTC->IRQ0 = 0xffffffff;
AINTC->IRQ1 = 0xffffffff;
PSCInit();
//Power and sleep control Init
//此处可以根据Harwboard的定义,修改设置,系统在运行的过程中按照指定的GPIO属性运行
SYSTEM->PINMUX[0] = 0x00007F55; // All Video Inputs
SYSTEM->PINMUX[1] = 0x00145555; // All Video Outputs
SYSTEM->PINMUX[2] = 0x00000004; // EMIFA
SYSTEM->PINMUX[3] = 0x1BFF55FF; // SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
SYSTEM->PINMUX[4] = 0x00000000; // MMC/SD0 instead of MS, SPI0
/******************* UART Setup **************************/
/******************* System PLL Setup ********************/
PLL1Init();
/******************* DDR PLL Setup ***********************/
PLL2Init();
/******************* DDR2 Timing Setup *******************/
DDR2Init();
/******************* AEMIF Setup *************************/
// Handled NAND init
AEMIFInit();
EVMDM355_I2C_init( );
UARTInit();
}
当上面这些初始化没有问题后,ubl在调用uboot运行。