Astro学习(1)Design & Timing setup

总的步骤是

1. design & Timing setup
2. floorplan
3. place
4. CTS
5. routing

1 建立布线环境
1.1 读入设计
Tools -> Data Prep

//======================Verilog================
Netlist in -> verilog to Cell

read verilog file
set library name
set output CELL name
set top module name
read tech file

add reference library use Rerference Library

use Global Net Options to set P/G net name

//=========================TLU+==============

Tech File -> ITF to TLU+
LPE mode choose MIN & MAX
enter min.tluplus & max.tluplus
enter map file

if want check -> sanity check

1.2 建立时序约束
Tools -> Astro

Timing -> Constraints: Load SDC           (before load use cmd "ataRemoveTC")
if want check:
Timing -> AstroTime: Timing Data Check...

因为在pre-CTS时不需要传播延时时钟和其他一些内部的连接的延时,并且为了节省时间delay model设为 Low Effort
Timing -> AstroTime: Timing Setup -> Model
   change Net Delay Model to Low Effort
Timing -> AstroTime: Timing Setup -> Envitonment
   Turn on the Ignore Interconect
   Turn on the Ignore Propagated Clock