BMS芯片BQ769x0芯片详解，结合手册

最新推荐文章于 2024-08-23 14:06:03 发布

koliko

最新推荐文章于 2024-08-23 14:06:03 发布

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分类专栏：硬件文章标签：嵌入式硬件硬件工程

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写在前面

本次芯片的解读是初学时边看手册边记录的，其中不免有许多错误以及自己的理解，还有许多内容没有完全写在里面，如果有别的需求的话大家还是需要认真阅读官方的手册，本博客只是手册里的一小部分。

本博客仅供参考

芯片模式

芯片具有两个模式，NORMAL为正常模式，此时电池正常工作，自动开启一些保护功能，SHIP为省电模式，需要给TS1引脚哦一个大于VBOOT的电平唤醒到NORMAL模式。

14bit ADC

采样速度

When any cells in a contiguous set of 5 cells are being balanced, those affected cells are measured in a reduced 12.5-ms decimation period, to allow the cell balancing to function properly without affecting the integrated OV and UV protections. Since cell balancing is typically only performed during pack charge or idle periods, the shortened decimation periods should not impact accuracy as the system noise during these times is greatly reduced. This reduced decimation period is only applied to sets where one of the cells is being balanced. The following summarizes this for the bq76920–bq76940 devices:

• VC1 to VC5 measurements are each taken in a 50-ms decimation period when all bits in CELLBAL1 register are 0, and a 12.5-ms decimation period when any bits in CELLBAL1 register are 1.

• VC6to VC10 measurements are each taken in a 50-ms decimation period when all bits in CELLBAL2 register are 0, and a 12.5-ms decimation period when any bits in CELLBAL2 register are 1.

• VC11to VC15 measurements are each taken in a 50-ms decimation period when all bits in CELLBAL3 register are 0, and a 12.5-ms decimation period when any bits in CELLBAL3 register are 1.

• Total update interval is 250 ms

当连续的5个电池中的任何一个正在进行平衡时，这些受影响的电池将在缩短为12.5毫秒的降采样周期内进行测量，以确保电池平衡功能正常运行而不影响集成过压和欠压保护。由于电池平衡通常只在充电期间或空闲期间执行，因此缩短的降采样周期不应对准确性产生影响，因为这些时间系统噪声大大降低。这种缩短的降采样周期仅适用于其中一个单元正在进行平衡操作的组合。以下是bq76920-bq76940设备相关内容总结：

意思就是，V0-V5这几个为一个电池组，当电池组里面有一个正在进行平衡操作的时候，采样的周期就会变短，即采样的频率会加快，12.5ms一个周期的速度及进行采样。平时的话就是50ms一个采样。所以平时的代码里面的话50ms采样一次应该就够了。

增益与偏置

Each differential cell input is factory-trimmed for gain and/or offset, such that the resulting reading via I2C is always consistent from part-to-part and requires no additional calibration or correction factor application. The ADC is required to be enabled in order for the integrated OV and UV protections to be operating. The following shows how to convert the 14-bit ADC reading into an analog voltage. Each device is factory calibrated, with a GAIN and OFFSET stored into EEPROM. The ADC transfer function is a linear equation defined as follows:

V(cell) = GAIN x ADC(cell) + OFFSET

每个电池差分单元都进行了出厂的微调，所以可以读取芯片寄存器里增益和偏置，然后利用公式算出ADC的值

/**
  * @brief  Get_offset 采集BQ76940的14位ADC的增益和偏置电压
  * @param  null
  * @retval null
  */
void Get_offset(void)
{
    unsigned char gain[2];

    gain[0] = IIC1_read_one_byte(ADCGAIN1); //ADC_GAIN1
    gain[1] = IIC1_read_one_byte(ADCGAIN2); //ADC_GAIN2
    ADC_GAIN = ((gain[0] & 0x0c) << 1) + ((gain[1] & 0xe0) >> 5); //12uV
    ADC_offset = IIC1_read_one_byte(ADCOFFSET); //45mV
    GAIN = 365 + ADC_GAIN; //GAIN=377uV
}

外部热敏电阻

BQ76940有3个热敏电阻的接口

One (bq76920), two (bq76930), or three (bq76940) 10 kΩ NTC 103AT thermistors may be measured by the device. These are measured by applying a factory-trimmed internal 10k pull-up resistance to an internal regulator value of nominally 3.3 V, the result of which can be read out from the TSx (TS1, TS2, TS3) registers.

内部是10k的上拉电阻

启用的话需要set [TEMP_SEL] = 1

连接方式如下

Thermistor TS1 is connected between TS1 and VSS; TS2 is connected between TS2 and VC5x (bq76930 and bq76940 only); and TS3 is connected between TS3 and VC10x (bq76940 only). These thermistors may be placed in various areas in the battery pack to measure such things as localized cell temperature, FET heating, etc.

可以放置在不同的区域，比如检测局部电池的温度，充放电的场效应管的温度等等。

模具温度监控

我的理解是可以检测电池里面的温度或者是芯片内部的温度

When switching between external and internal temperature monitoring, a 2-s latency may be incurred due to the natural scheduler update interval

在外部温度检测以及模具温度检测切换时会有2s延迟

启用的话需要set [TEMP_SEL] = 0

看的不太清楚，暂时不考虑使用

系统调度 System Scheduler

A master scheduler oversees the monitoring intervals, creating a full update every 250 ms. Temperature measurements are taken every 2 seconds. Pack voltage is calculated every 250 ms.

250ms完成一次完整的更新，2s完成一次温度的采集

保护子系统 Protection Subsystem

集成硬件保护 Integrated Hardware Protections

芯片自带的硬件保护，但是不应该作为保护电池的唯一手段，算是一种保险手段。

Overcurrent in Discharge (OCD) and Short Circuit in Discharge (SCD) are implemented using sampled analog comparators that run at 32 kHz, and that continuously monitor the voltage across (SRP–SRN) while the device is in NORMAL mode. Upon detection of a voltage that exceeds the programmed OCD or SCD threshold, a counter begins to count up to a programmed delay setting. If the counter reaches its target value, the SYS_STAT register is updated to indicate the fault condition, the FET state(s) are updated as shown in

过流以及短路硬件检测，会使用一个计数器，当计数器大于某个值则自动触发

The protection fault threshold and delay settings for OCD and SCD protections are configured via the PROTECT1 and PROTECT2 registers

保护的值设置在PROTECT1和PROTECT2寄存器当中

过充以及过放硬件保护

Overvoltage (OV) and Undervoltage (UV) protections are handled digitally, by comparing the cell voltage readings against the 8-bit programmed thresholds in the OV and UV registers.

The OV threshold is stored in the OV_TRIP register and is a direct mapping of 8 bits of the 14-bit ADC reading, with the upper 2 MSB preset to “10” and lower 4 LSB preset to “1000”. In other words, the corresponding OV trip level is mapped to “10-XXXX-XXXX–1000”. The programmable range of OV thresholds is approximately 3.15 to 4.7 V, but this is subject to variation due to the (GAIN, OFFSET) linear equation used to map the ADC values.

The UV threshold is stored in the UV_TRIP register and is a direct mapping of 8 bits of the 14-bit ADC reading, with the upper 2 MSB preset to “01” and lower 4 LSB preset to “0000”. In other words, the corresponding OV trip level is mapped to “01-XXXX-XXXX–0000”. The programmable range of UV thresholds is approximately 1.58 to 3.1 V, but this is subject to variation due to the (GAIN, OFFSET) linear equation used to map the ADC values.

正确计算设备的OV_TRIP和UV_TRIP寄存器的值，需要以下步骤

确定期望的OV
从相应的寄存器中读出[ADCGAIN]和[ADCOFFSET]。注意储存的单位！！！
计算OV和UV跳闸阈值完整的14位ADC
1. OV_TRIP_FULL = (OV - ADCOFFSET) ADCGAIN
2. UV_TRIP_FULL = (UV - ADCOFFSET) ADCGAIN
从完整的14位值中删除上部2 MSB以及下部4 USB
将其写入相应寄存器

这种保护要建立在 [ADC_EN] 被设置为 1 的条件下

Reduced Test Time ：A special debug and test configuration bit is provided in the SYS_CTRL2 register, called [DELAY_DIS]. Setting [DELAY_DIS] bypasses the OV/UV protection fault timers and allows a fault condition to be registered within 200 ms after application of such a fault condition.

芯片利用设置 [DELAY_DIS] 位可以缩短测试的时间，就可以免去达到阈值的持续时间，直接测试是否有效。

控制子系统

场效应晶体管驱动 FET Driving (CHG AND DSG)

CHG控制充电MOS，DSG控制放电MOS

电路原理

Both DSG and CHG drivers have a fast pull-up to nominally 12 V when enabled. DSG uses a fast pull down to VSS when disabled, while CHG utilizes a high impedance (nominally 1 MΩ) pull-down path when disabled.

The power path for the CHG and DSG pull-up circuit originates from the REGSRC pin, instead of BAT. To enable the CHG fet, set the [CHG_ON] register bit to 1; to disable, set [CHG_ON] = 0. The discharge FET may be similarly controlled via the [DSG_ON] register bit. Certain fault conditions or power state transitions will clear the state of the CHG/DSG FET controls. 表 7-1 shows what action, if any, to take to [CHG_ON] and [DSG_ON] in response to various system events:

[CHG_ON]和[DSG_ON]分别控制两个引脚，一些特殊事件也会清空这俩标志位

EVENT	[CHG_ON]	[DSG_ON]
OV Fault	Set to 0	-
UV Fault	-	Set to 0
OCD Fault	-	Set to 0
SCD Fault	-	Set to 0
ALERT Override	Set to 0	Set to 0
DEVICE_XREADY is set	Set to 0	Set to 0
Enter SHIP mode from NORMAL	Set to 0	Set to 0

注意：有些情况特殊情况需要先清除SYS_STAT寄存器（同时会清除ALER引脚），在进行CHG DSG的操作

电池均衡 Cell Balancing

bq76920完全支持内部和外部被动电池均衡选项，而对于bq76930和bq76940，则建议使用外部电池均衡。具体在任何给定系统中使用哪种均衡算法由主控制器决定。每个bq769x0设备都提供了单体电压和均衡驱动器以实现这一功能。如果使用内部的单体平衡驱动器，每个单体最多可以平衡50mA。如果使用外部的单体平衡，可以采用更高的平衡电流。

要激活特定的单体均衡通道，只需设置CELLBAL1、CELLBAL2或CELLBAL3寄存器中相应单元的位。例如，通过设置[CB1]来启用VC1-VCO通道，而通过[CB12]来设置VC12-VC11通道。

可以同时对多个单元进行平衡。用户可自行决定同时进行平衡的理想数量。不应同时对相邻的单元进行平衡操作！这可能导致单元引脚超过其绝对最大条件，并且也不推荐在外部均衡实现中这样做。此外，如果使用内部均匀化处理，请注意避免超过封装功耗额定值。

警报 Alert

The ALERT pin serves as an active high digital interrupt signal that can be connected to a GPIO port of the host microcontroller. This signal is an OR of all bits in the SYS_STAT register.

ALERT 引脚的信号是SYS_STAT 寄存器所有位的或

In order to clear the ALERT signal, the source bit in the SYS_STAT register must first be cleared by writing a “1” to that bit.

清除警报引脚需要给SYS_STAT 寄存器源位写1

注：

强烈建议将外部500 kΩ-1 ΜΩ从ALERT到VSS的下拉电阻且尽可能靠近IC。

其他建议是:

A. 保持IC和连接到ALERT引脚的组件之间的所有走线非常短。

B. 在连接到ALERT引脚和引脚本身的组件周围包括保护环。

输出LDO

An adjustable output voltage regulator LDO is provided as a simple way to provide power to additional components in the battery pack, such as the host microcontroller or LEDs. The LDO is configured in EEPROM by TI during the production test process, and can support 2.5-V or 3.3-V options.

LDO输出支持2.5V-3.3V出厂配置在ROM里面

必须在BAT和REGSRC之间的外部路径上添加一个级联小信号场效应管，使用bq76930和bq76940。

这有助于降低封装外部的大部分功耗，降低封装功耗。

通信子系统

该AFE实现了标准的100khz 12C接口，并充当从设备。

I2C设备地址是7位的

芯片模式

NORMAL Mode

正常模式表示完全操作模式，其中所有块都是启用的，设备可以看到它的最高电流消耗。在这种模式下，某些块/函数可能会被禁用以保存电源包括ADC和CC，只要ADC在，OV和UV就会持续运行启用。在此模式下，OCD和SCD比较器不能被禁用。从NORMAL模式到SHIP模式的转换也是由主机发起的，并且需要连续写入SYS_CTRL1寄存器中的两位。

SHIP Mode

SHIP模式是bq769x0支持的基本和最低功耗模式。SHIP模式自动在初次装配时和每次POR事件（上电复位）后启用。当设备处于NORMAL模式时，它可以通过特定的I2C命令序列由主控制器进入SHIP。在SHIP模式下，只有最少的模块被打开，包括VSTUP电源和基本引导探测器。从SHIP模式唤醒到NORMAL模式需要拉动TS1引脚大VBOOT，触发设备启动顺序。

要从NORMAL模式进入SHIP模式，SYS_CTRL1寄存器中的[SHUT_A]和[SHUT_B]位

必须在两个连续的写入中以特定的模式写入:

• Write #1: [SHUT_A] = 0, [SHUT_B] = 1

• Write #2: [SHUT_A] = 1, [SHUT_B] = 0

注意，在执行shutdown命令之前，[SHUT_A]和[SHUT_B]都应该处于0状态。如果在设备中输入这个特定的序列，设备将转换到SHIP模式。如果有任何其他序列被写入[SHUT_A]和[SHUT_B]位，或者两个模式中的任何一个没有被写入正确输入，设备将不会进入SHIP模式

需要注意，每组电池组的电压不能低于VSHUT