2024年秋招-芯原数字IC笔试题

3.As we know, handshake is a way to make sure data correctly transter through pipline. lt constructs of validready/acknowledge signal and data to be tansferred. Please design one handshake delay method. in whichcombinational logic of valid and acknowledge signal are parted by flip-flop respectively to improve timning. (6 scores）

module handshake_delay(
    input clk,
    input reset_n,
    input in_val,                       //from pre-stage
    input [c_dw_in-1:0] in_data,        //from pre-stage
    output in_ack,                      //to pre-stage

    output out_val,                     //to post-stage
    output [c_dw_in-1:0] out_data,      //to post-stage
    input out_ack                       //from post-stage
);

reg in_ack_r;
reg out_val_r;
reg out_data_r;

always @ (posedge clk) begin
    if (!reset_n) 
        in_ack_r <= 0;
    else if (in_val)
        in_ack_r <= 1;
    else
        in_ack_r <=