lichunpu_001的专栏

OMAP3525 and OMAP3530 Applications – Additional C64x+™ Enhancements Processors: · Protected Mode Operation – OMAP™ 3 Architecture · Exceptions Support for Error Detection – MPU Subsystem and Program Redirection · 600-MHz ARM Cortex™-A8 Core · Hardware Support for Modulo Loop · NEON™ SIMD Coprocessor Operation – High Performance Image, Video, Audio · C64x+ L1/L2 Memory Architecture (IVA2.2™) Accelerator Subsystem – 32K-Byte L1P Program RAM/Cache (Direct · 430-MHz TMS320C64x+™ DSP Core Mapped) · Enhanced Direct Memory Access – 80K-Byte L1D Data RAM/Cache (2-Way (EDMA) Controller (128 Independent Set-Associative) Channels) – 64K-Byte L2 Unified Mapped RAM/Cache · Video Hardware Accelerators (4-Way Set-Associative) – POWERVR SGX™ 2D/3D Graphics – 32K-Byte L2 Shared SRAM and 16K-Byte L2 Accelerator (OMAP3530 Device Only) ROM · Tile Based Architecture Delivering up to · C64x+ Instruction Set Features 10 MPoly/sec – Byte-Addressable (8-/16-/32-/64-Bit Data) · Universal Scalable Shader Engine: – 8-Bit Overflow Protection Multi-threaded Engine Incorporating – Bit-Field Extract, Set, Clear Pixel and Vertex Shader Functionality – Normalization, Saturation. Bit-Counting · Industry Standard API Support: – Compact 16-Bit Instructions OpenGLES 1.1 and 2.0, OpenVG1.0 – Additional Instructions to Support Complex · Fine Grained Task Switching, Load Multiplies Balancing, and Power Management · Programmable High Quality Image · ARM Cortex™-A8 Core Anti-Aliasing – ARMv7 Architecture – Fully Software-Compatible With C64x and · Trust Zone® ARM9™ · Thumb®-2 – Commercial and Extended Temperature · MMU Enhancements Grades – In-Order, Dual-Issue, Superscalar · Advanced Very-Long-Instruction-Word (VLIW) Microprocessor Core TMS320C64x+™ DSP Core – NEON™ Multimedia Architecture – Eight Highly Independent Functional Units – Over 2x Performance of ARMv6 SIMD · +Six ALUs (32-/40-Bit), Each Supports – Supports Both Integer and Floating Point Single 32-Bit, Dual 16-Bit, or Quad 8-Bit SIMD Arithmetic per Clock Cycle – Jazelle® RCT Execution Environment · Two Multipliers Support Four 16 x 16-Bit Architecture Multiplies (32-Bit Results) per Clock – Dynamic Branch Prediction with Branch Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Target Address Cache, Global History Results) per Clock Cycle Buffer, and 8-Entry Return Stack – Load-Store Architecture With Non-Aligned – Embedded Trace Macrocell (ETM) Support Support for Non-Invasive Debug – 64 32-Bit General-Purpose Registers · ARM Cortex™-A8 Memory Architecture: – Instruction Packing Reduces Code Size – 16K-Byte Instruction Cache (4-Way – All Instructions Conditional

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