tlb(Translation Look-Aside Buffer)

Translation Look-aside Buffer (TLB) is cache in a CPU that contains parts of the page table which translate from virtual into real addresses. This buffer has a fixed number of entries and is used to improve the speed of virtual address translation. The buffer is typically a content addressable memory (CAM) in which the search key is the virtual address and the search result is a real or physical address (which, perversely, may not be the same thing). If the CAM search yields a match the translation is known and the match data is used. If no match exists, the translation proceeds via the page table, which will take several more cycles to complete – particularly if the translation tables are swapped out into secondary storage. The TLB enables faster computing because it allows the address processing to take place independent of the normal address-translation pipeline.