奇数分频器之三分之一分频器源码和仿真

#源码#

在clk上升沿和下降沿的时候也计数。

module half_clk(reset,clk_in,clk_out);

  input clk_in,reset;

  output clk_out;

  reg clk_out;

   reg[1:0] clk_posedge_cnt = 2'd0;

   always @(posedge clk_in or negedge clk_in)

   begin

    clk_posedge_cnt = clk_posedge_cnt + 2'd1;

    if(!reset) clk_out = 0;

    else if(clk_posedge_cnt === 2'd3)

    begin

      clk_out = ~clk_out;

      clk_posedge_cnt = 0;

    end      

   end

    

endmodule

#仿真#

`timescale 1ns / 100ps

`define clk_cycle 50

module top;

reg clk,reset;

wire clk_out;

always #`clk_cycle clk = ~clk;

initial

begin

  clk = 0;

  reset = 1;

  #10 reset = 0;

  #110 reset = 1;

  #10000 $stop;

end

  half_clk m0(.reset(reset),.clk_in(clk),.clk_out(clk_out));

endmodule

#波形#