奇分频和偶分频

`timescale 1ns / 1ps
时钟的分频与倍频
/*
50M - 100M    t = 20ns    T = 10ns
奇分频 ：50M-10M   5
偶分频 ：50M-5M   50M   T = 20ns   5M   t = 200ns     10
实现方式：
（1）计时器
（2）PLL（锁相环：IP）
*/
module test_clk(
    input           sysclk              ,
    input           rst_n               ,
    output  wire     clk_odd             ,  奇分频  5
    output  reg     clk_even               偶分频   10
    );
//偶分频
reg     [4:0]      cnt_e   ;
always@(posedge sysclk)
    if(!rst_n)
        cnt_e <= 0;
    else if(cnt_e == 9)
        cnt_e <= 0;
    else
        cnt_e <= cnt_e + 1;
always@(posedge sysclk)
    if(!rst_n)
        clk_even <= 0;
    else if(cnt_e == 4 || cnt_e == 9)  
        clk_even <= ~clk_even;
    else
        clk_even <= clk_even; 
//奇分频
reg     [2:0]       cnt1        ;
reg     [2:0]       cnt2        ;
reg                 clk1        ;
reg                 clk2        ;
parameter          n = 5        ;
///clk1
always@(posedge sysclk)
    if(!rst_n)
        cnt1 <= 0;
    else if(cnt1 == 4)
        cnt1 <= 0;
    else
        cnt1 <= cnt1 + 1;
always@(posedge sysclk)
    if(!rst_n)
        clk1 <= 1;
    else if(cnt1 == n -1 || cnt1 == (n-1)/2 - 1)
        clk1 <= ~clk1;
    else
        clk1 <= clk1;
/clk2
always@(negedge sysclk)
    if(!rst_n)
        cnt2 <= 4;
    else if(cnt2 == 4)
        cnt2 <= 0;
    else
        cnt2 <= cnt2 + 1;
always@(negedge sysclk)
    if(!rst_n)
        clk2 <= 0;
    else if(cnt2 == n -1 || cnt2 == (n-1)/2 - 1)
        clk2 <= ~clk2;
    else
        clk2 <= clk2;
assign  clk_odd = clk1 | clk2;
endmodule

仿真代码：

`timescale 1ns / 1ps
module odd_tb( );
       reg      sysclk              ;
       reg      rst_n               ;
       wire     clk_odd             ;
       wire     clk_even            ;
       
  initial begin
    
    sysclk = 0 ;
    rst_n =  0 ;
    
    #20   rst_n =1 ;
    
  
  end   
  
  always #10  sysclk = ~sysclk  ;    /20ns
       
  

test_clk  test_clk1(
             .   sysclk      (sysclk   )        ,
             .   rst_n       (rst_n    )        ,
             .    clk_odd    ( clk_odd )         ,  奇分频  5
             .   clk_even    (clk_even )           偶分频   10
    );
    




endmodule

仿真结果：