TOP module
module top(
input clk100mhz,
input clr,
input s,
input key1,
input key2,
input key3,
input key4,
input [2:0]count1,
output [3:0] pos1,
output [3:0] pos2,
output [7:0] seg1,
output [7:0] seg2
);
wire [3:0]data;
wire clk190hz, clk3hz;
wire [15:0]dataBus1;
wire [15:0]dataBus2;
clkDiv U1(clk100mhz, clk190hz, clk3hz);
GPU U2(.clk3hz(clk3hz), .clr(clr),.s(s),.n(data),.w(count1),.dataBus1(dataBus1),.dataBus2(dataBus2));
segMsgout1 U3(clk190hz,dataBus1, pos1, seg1);//输入显示数码管
segMsgout2 U4(clk190hz,dataBus2, pos2, seg2);//输出显示数码管
Pushin U5(key1,key2,key3,key4,s,clr,count1,clk100mhz,data);
endmodule
clkDiv module
module clkDiv(
input clk100mhz,
output clk190hz,
output clk3hz
);
reg [25:0]count=0;
assign clk190hz=count[18];
assign clk3hz=count[25];
always@(posedge clk100mhz)
count<=count+1;
endmodule
GPU module
module GPU(
input clk3hz,
input clr,
input s,
input [3:0]n,
input [2:0]w,
output reg [15:0]dataBus1,
output reg [15:0]dataBus2
);
reg [31:0]msgArray;
always@(posedge clk3hz or posedge clr)
begin
if(!clr) //清零功能
begin
dataBus1<=16'b1100_1100_1100_1100;
dataBus2<=16'b1010_1010_1010_1010;
end
else
begin
if(s) //输入的值传入输出
begin
dataBus1 <= 16'b1100_1100_1100_1100;
dataBus2 <= msgArray[31:16];
end
else
begin
dataBus2<=16'b1010_1010_1010_1010;
if(w>=4)
dataBus1<=msgArray[15:0];
else
dataBus1<=msgArray[31:16];
end
end
end
always@(posedge clk3hz or posedge clr)
begin
if(!clr)
begin
msgArray <= 32'b1111_1111_1111_1111_1111_1111_1111_1111;
end
else
begin
if(s) //移位操作:将高四位移动到低四位,同时将27-0位移动到31-4位,这样便实现了一个数据的移动
begin
msgArray[3:0]<=msgArray[31:28];
msgArray[31:4]<=msgArray[27:0];
end
else
case(w)
0:msgArray[31:28] <= n[3:0];
1:msgArray[27:24] <= n[3:0];
2:msgArray[23:20]<= n[3:0];
3:msgArray[19:16]<= n[3:0];
4:msgArray[15:12]<= n[3:0];
5:msgArray[11:8]<= n[3:0];
6:msgArray[7:4] <= n[3:0];
7:msgArray[3:0] <= n[3:0];
default:msgArray[31:0]=32'b1111_1111_1111_1111_1111_1111_1111_1111;
endcase
end
end
endmodule
segMsgout1 module
module segMsgout1(
input clk190hz,
input [15:0] dataBus,
output reg [3:0] pos,
output reg [7:0] seg
);
reg [1:0] posC;
reg [3:0] dataP;
always @(posedge clk190hz )begin
case(posC)
0: begin
pos<=4'b1000;
dataP<=dataBus[15:12];
end
1:begin
pos <=4'b0100;
dataP <= dataBus[11:8];
end
2:begin
pos <=4'b0010;
dataP <= dataBus[7:4];
end
3:begin
pos <=4'b0001;
dataP <= dataBus[3:0];
end
endcase
posC = posC + 2'b01;
end
always @(dataP)
case(dataP)
4'b0000:seg=8'b0011_1111;
4'b0001:seg=8'b0000_0110;
4'b0010:seg=8'b0101_1011;
4'b0011:seg=8'b0100_1111;
4'b0100:seg=8'b0110_0110;
4'b0101:seg=8'b0110_1101;
4'b0110:seg=8'b0111_1101;
4'b0111:seg=8'b0000_0111;
4'b1000:seg=8'b0111_1111;
4'b1001:seg=8'b0110_1111;
4'b1010:seg=8'b0100_0000;
4'b1011:seg=8'b0000_0000;
default:seg=8'b0000_1000;
endcase
endmodule
segMsgout2 module
module segMsgout2(
input clk190hz,
input [15:0] dataBus,
output reg [3:0] pos,
output reg [7:0] seg
);
reg [1:0] posC;
reg [3:0] dataP;
always @(posedge clk190hz )begin
case(posC)
0: begin
pos<=4'b1000;
dataP<=dataBus[15:12];
end
1:begin
pos <=4'b0100;
dataP <= dataBus[11:8];
end
2:begin
pos <=4'b0010;
dataP <= dataBus[7:4];
end
3:begin
pos <=4'b0001;
dataP <= dataBus[3:0];
end
endcase
posC = posC + 1;
end
always @(dataP)
case(dataP)
4'b0000:seg=8'b0011_1111;
4'b0001:seg=8'b0000_0110;
4'b0010:seg=8'b0101_1011;
4'b0011:seg=8'b0100_1111;
4'b0100:seg=8'b0110_0110;
4'b0101:seg=8'b0110_1101;
4'b0110:seg=8'b0111_1101;
4'b0111:seg=8'b0000_0111;
4'b1000:seg=8'b0111_1111;
4'b1001:seg=8'b0110_1111;
4'b1010:seg=8'b0100_0000;
4'b1011:seg=8'b0000_0000;
default:seg=8'b0000_1000;
endcase
endmodule
Pushin module
module Pushin(
input key1,
input key2,
input key3,
input key4,
input s,
input clr,
input [2:0]count0,
input clk,
output reg[3:0]data
);
always@(posedge clk)
begin
data[3:0]<={key4,key3,key2,key1};
end
endmodule
其中几个模块功能有所重复,可以优化一下