VHDL实现加法器

//全加法器
library ieee;
use ieee.std_logic_1164.all;
entity alladder is
port(
A,B,Cin:in std_logic;
S,Cout:out std_logic
);
end entity alladder;
architecture adderfunc of alladder is
begin

Cout<=((A xor B) AND Cin) OR (A AND B);

END;

//四位并行加法器
library ieee;
use ieee.std_logic_1164.all;
entity sequenadder is
port(
A:IN BIT_VECTOR(3 DOWNTO 0);
B:IN BIT_VECTOR(3 DOWNTO 0);
Cin:IN BIT;
S:OUT BIT_VECTOR(4 DOWNTO 0)
);
END;
ARCHITECTURE SEQUENFUNC OF sequenadder IS
SIGNAL SIN1:BIT;
SIGNAL SIN2:BIT;
SIGNAL SIN3:BIT;
COMPONENT alladder IS
PORT(
A,B,Cin:IN BIT;
S,Cout:OUT BIT
);
END COMPONENT;
BEGIN
G1:alladder port map(A=>A(0),B=>B(0),Cin=>Cin,S=>S(0),Cout=>SIN1);
G2:alladder port map