MT7628中CHIP_MODE[2:0] 模式配置全解析

CHIP_MODE[2:0] 模式配置全解析

CHIP_MODE[2:0] 是一个3位硬件配置字段,通过组合 启动时钟源(PLL/XTAL)SPI Flash地址模式(3-Byte/4-Byte) 定义芯片的启动行为。以下是所有模式的详细说明及对比:

模式定义与核心功能
二进制值 模式名称 启动时钟源 SPI地址模式 适用场景
000 PLL + SPI 3-Byte 内部PLL 3-Byte(24位地址) 快速启动,小容量Flash(≤16MB)
001 PLL + SPI 4-Byte 内部PLL 4-Byte(32位地址) 大容量Flash(>16MB)需高速初始化
010 XTAL + SPI 3-Byte 外部晶体 3-Byte(24位地址) 高精度时钟,小容量稳定系统
011 XTAL + SPI 4-Byte 外部晶体 4-Byte(32位地址) 高精度时钟+大容量存储

1. 硬件配置要点

1.1 时钟源选择(PLL vs XTAL)
时钟源 特性 硬件设计要求
PLL - 依赖芯片内部锁相环倍频
- 启动速度快,但可能存在初始频率抖动
- 确保电源稳定性(PLL对噪声敏感)
- 无需外部晶体电路
XTAL - 依赖外部晶体振荡器
- 时钟精度高,稳定性强,但起振时间较长
MT6363 EXT_PMIC_PG [PMIC]PG_SDN_STS0_1[0x20B]=0xFFFF [PMIC]PG_SDN_STS2_3[0x20D]=0xFFFF [PMIC]PG_SDN_STS4[0x20F]=0x0 [PMIC]TOPSTATUS[0x1E]=0x1A [PMIC]VR_SDN_MODE0_1[0x214]=0x0 [PMIC]VR_SDN_MODE2_3[0x216]=0x0 [PMIC]VR_SDN_MODE4_5[0x218]=0x10 [PMIC]VR_SDN_MODE6_7[0x21A]=0x0 [PMIC]STS_THR_LOC[0x10]=0x0 [PMIC]STRUP_CON4[0xA1A]=0x0 [PMIC]STRUP_CON12[0xA0F]=0x51 [PMIC]WDTRSTB[0x139]=0x0 [PMIC]just_rst = 0 [MT6363] latch VS2 1275000 uV(0x55) [MT6363] latch VBUCK1 0 uV(0x0) [MT6363] latch VBUCK2 0 uV(0x0) [MT6363] latch VBUCK4 1125000 uV(0xEE) [MT6363] latch VBUCK5 500000 uV(0x78) [MT6363] latch VBUCK6 500000 uV(0x78) [MT6363] latch VS1 1887500 uV(0xDC) [MT6363] latch VS3 950000 uV(0xD4) [MT6363] latch VSRAM_DIGRF 400000 uV(0x0) [MT6363] latch VSRAM_MDFE 400000 uV(0x0) [MT6363] latch VSRAM_MODEM 750000 uV(0x24) [MT6363] latch VSRAM_CPUB 756250 uV(0x24) [MT6363] latch VSRAM_CPUM 400000 uV(0x0) [MT6363] latch VSRAM_CPUL 750000 uV(0x24) [MT6363] latch VSRAM_APU 400000 uV(0x0) [pwrkey_dbg_status] powerkey:0 count=0(ms) g_pwrkey_release=1 [pmic_wdt_set]WDTRSTB[0x139]=0x21 pmic_auxadc_device_register main_pmic successfully pmic_auxadc_device_register main_pmic_sdmadc successfully AUXADC_CHAN_CHIP_TEMP:677 AUXADC_CHAN_VCORE_TEMP:678 AUXADC_CHAN_VPROC_TEMP:682 AUXADC_CHAN_VGPU_TEMP:673 [MT6319]S6 RG_SLV_ID[0x136]=0xB6 [MT6319]S6 POFFSTS[0xC]=0x0 [MT6319]S6 RGS_POFFSTS[0xA0F]=0x14 [MT6319]S6 PG_SDN_STS0[0xF]=0xF [MT6319]S6 OC_SDN_STS0[0x10]=0x0 [MT6319]S6 BUCK_OC_SDN_STS[0x1416]=0x0 [MT6319]S6 BUCK_OC_SDN_EN[0x1451]=0x1F [MT6319]S6 TOP_RST_MISC[0x126]=0x0 0xFFFF:0xFFFF:0xFFFF:0xFFFF:0x88:0x4118:0xEFF2:0x6A43:(S6) [MT6319]S6 set seq off=0 [MT6319]latch vmm 0 uV(0x0) [MT6319]latch vgpu 0 uV(0x0) [MT6319]latch vapu 0 uV(0x0) [MT6319]latch vcore 0 uV(0x0) [MT6319]S6 TOP_RST_MISC=0x0 [MT6319]S6 set TOP_RST_MISC=0x3 [MT6319]MT6319 init_setting end. v231004 [MT6319]mt6319_spmi_probe done [second_pmic_check_cid] CHIP Code=0x6921 record write addr=0x190, data=0x7, cmd=3 record write addr=0x191, data=0x40, cmd=3 record write addr=0x190, data=0xF, cmd=3 record write addr=0x191, data=0x40, cmd=3 record write addr=0x190, data=0x7, cmd=3 record write addr=0x191, data=0x40, cmd=3 record write addr=0x190, data=0x3, cmd=3 record write addr=0x191, data=0x40, cmd=3 record write addr=0x190, data=0x1, cmd=3 record write addr=0x191, data=0x40, cmd=3 record write addr=0x190, data=0x81, cmd=3 record write addr=0x191, data=0x42, cmd=3 record write addr=0x190, data=0x1, cmd=3 record write addr=0x191, data=0x42, cmd=3 record write addr=0x190, data=0x1, cmd=3 record write addr=0x191, data=0x40, cmd=3(the last) [SECOND_PMIC]PONSTS[0xC]=0x40 [SECOND_PMIC]POFFSTS0_1[0xD]=0x0 [SECOND_PMIC]POFFSTS2_3[0xF]=0x2 [SECOND_PMIC]POFFSTS4_5[0x11]=0x4001 [SECOND_PMIC]POFFSTS6[0x13]=0xC [SECOND_PMIC]VR_SDN_MODE0_1[0x20D]=0x5 [SECOND_PMIC]VR_SDN_MODE2_3[0x20F]=0x0 [SECOND_PMIC]VR_SDN_MODE4_5[0x211]=0x40 [SECOND_PMIC]WDTRSTB[0x139]=0x0 [MT6369] latch VBUCK1 750000 uV(0x44) [MT6369] latch VPA 600000 uV(0x3) [MT6369] latch VSRAM_CORE 750000 uV(0x24) [MT6369] latch VDIGRF 550000 uV(0x14) [second_pmic_wdt_set]WDTRSTB[0x139]=0x21 pmic_auxadc_device_register second_pmic successfully pmic_auxadc_device_register second_pmic_sdmadc successfully [SECOND_PMIC] vm_mode=0xFFFFFFFF. Init done. [PMIC]Init done [pmic_enable_smart_reset] smart_en:0, smart_sdn_en:0 #T#PMIC=56 Enter mtk_kpd_gpio_set! mtk detect key function pmic_detect_homekey MTK_PMIC_RST_KEY = 17 Log Turned Off. #T#UART DYNAMIC SWITCH=34 PL_LOG_STORE, last PMIC boot up phase is 0x99:0x990. PL_LOG_STORE, last boot up phase is 9, return 0. #T#LOGSTORE_BOOT=1 mt6685_adc_init start [MT6685]PONSTS[0xC]=0x1 [MT6685]POFFSTS0_1[0xD]=0x800 [MT6685]RGS_FAULT[0xA0C][3:1]=0x1 [MT6685]PG_OC_SDN_STS0[0x13]=0x7F [MT6685]STS_PDN_MODE0_1[0x15]=0x4001 MT6685 TOP_RST_MISC=0x4++ before MT6685_RG_DCXO_AAC_ELR_1=0x1 before MT6685_DDLO_EN=0x98 before MT6685_RG_UVLO_VTHL_ADDR=0x0 MT6685HP_ECID:46353 38257 40349 13553 MT6685 TOP_RST_MISC=0x7-- mt6685_adc_init end. v210623
10-22
UINT32 mt_rx_pkt_process(RTMP_ADAPTER *pAd, UINT8 resource_idx, RX_BLK *rx_blk, PNDIS_PACKET rx_packet) { UINT32 rx_pkt_type; enum resource_attr res_attr = hif_get_resource_type(pAd->hdev_ctrl, resource_idx); if (res_attr == HIF_RX_DATA) rx_pkt_type = asic_get_packet_type(pAd, GET_OS_PKT_DATAPTR(rx_packet)); else { rx_pkt_type = asic_get_packet_type(pAd, rx_packet); /* rx data is from event ring, convert it to skb */ if (rx_pkt_type == RMAC_RX_PKT_TYPE_RX_NORMAL || rx_pkt_type == RMAC_RX_PKT_TYPE_RX_DUP_RFB) { PNDIS_PACKET pkt = NULL; DEV_ALLOC_SKB(pkt, RX1_BUFFER_SIZE); if (pkt) { NdisCopyMemory(OS_PKT_TAIL_BUF_EXTEND(pkt, RX1_BUFFER_SIZE), rx_packet, RX1_BUFFER_SIZE); rx_packet = pkt; hif_free_rx_buf(pAd->hdev_ctrl, resource_idx); } else { hif_free_rx_buf(pAd->hdev_ctrl, resource_idx); return NDIS_STATUS_SUCCESS; } } } /*notify to interesting feature, only enable when DVT mode enable*/ call_traffic_rx_notifierieres(pAd, rx_pkt_type, rx_packet); #ifndef ZTE MTWF_DBG(pAd, DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_INFO, "%s, rx_pkt_type(%d)\n", __func__, rx_pkt_type); #endif switch (rx_pkt_type) { case RMAC_RX_PKT_TYPE_RX_NORMAL: case RMAC_RX_PKT_TYPE_RX_DUP_RFB: rx_data_handler(pAd, rx_blk, rx_packet); break; case RMAC_RX_PKT_TYPE_RX_TXRXV: #ifdef CONFIG_ICS_FRAME_HANDLE if (pAd->rxvIcs == 0) asic_rxv_handler(pAd, rx_blk, rx_packet); #else asic_rxv_handler(pAd, rx_blk, rx_packet); #endif /* CONFIG_ICS_FRAME_HANDLE */ hif_free_rx_buf(pAd->hdev_ctrl, resource_idx); break; case RMAC_RX_PKT_TYPE_RX_TXS: chip_txs_handler(pAd, rx_packet); hif_free_rx_buf(pAd->hdev_ctrl, resource_idx); break; case RMAC_RX_PKT_TYPE_RX_EVENT: asic_rx_event_handler(pAd, rx_packet); RX_BLK_SET_FLAG(rx_blk, fRX_CMD_RSP); hif_free_rx_buf(pAd->hdev_ctrl, resource_idx); break; case RMAC_RX_PKT_TYPE_RX_TMR: /* tmr_handler(pAd, rx_blk, rx_packet); */ hif_free_rx_buf(pAd->hdev_ctrl, resource_idx); break; #ifdef CUT_THROUGH case RMAC_RX_PKT_TYPE_TXRX_NOTIFY: #ifdef WFDMA_WED_COMPATIBLE case RMAC_RX_PKT_TYPE_TXRX_NOTIFY_V0: #endif /*WFDMA_WED_COMPATIBLE*/ asic_txdone_handle(pAd, rx_packet, resource_idx); hif_free_rx_buf(pAd->hdev_ctrl, resource_idx); break; #endif /* CUT_THROUGH */ case RMAC_RX_PKT_TYPE_RX_ICS: #ifdef CONFIG_ICS_FRAME_HANDLE if (pAd->rxvIcs) chip_rx_ics_handler(pAd, DBG_LOG_PKT_TYPE_ICS, rx_packet, 0); #endif /* CONFIG_ICS_FRAME_HANDLE */ #ifdef FW_LOG_DUMP dbg_log_wrapper(pAd, DBG_LOG_PKT_TYPE_ICS, rx_packet, 0); #endif /* FW_LOG_DUMP */ RELEASE_NDIS_PACKET(pAd, rx_packet, NDIS_STATUS_SUCCESS); break; default: MTWF_DBG(pAd, DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_ERROR, "%s():Invalid PktType:%d (res_attr:%d)\n", __func__, rx_pkt_type, res_attr); if (res_attr != HIF_RX_DATA) hif_free_rx_buf(pAd->hdev_ctrl, resource_idx); else RELEASE_NDIS_PACKET(pAd, rx_packet, NDIS_STATUS_FAILURE); break; } return NDIS_STATUS_SUCCESS; }
最新发布
12-10
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