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sv define ``的用法
sv define ``的用法https://www.design-reuse.com/articles/45979/system-verilog-macro-a-powerful-feature-for-design-verification-projects.html原创 2020-02-28 13:42:13 · 4150 阅读 · 0 评论 -
Verilog/SystemVerilog中==和===的区别
https://stackoverflow.com/questions/5927615/what-is-the-difference-between-and-in-verilogA : if (dataoutput[7:0] == 8’bx) beginB : if (dataoutput[7:0] === 8’bx) beginAfter executing dataoutput = 52...原创 2020-03-02 20:22:35 · 7767 阅读 · 1 评论