tiny210（s5pv210）DDR2的初始化

做一个裸机测试内存DDR2的小程序，找了好多，没有找到类似的，只能静下心来看三星给的文档了！

三星文档描述（P598）：

Initialization sequence for DDR2 memory type:
1. To provide stable power for controller and memory device, the controller must assert and hold CKE to a logic low level. Then apply stable clock. Note: XDDR2SEL should be High level to hold CKE to low.
2. Set the PhyControl0.ctrl_start_point and PhyControl0.ctrl_inc bit-fields to correct value according to clock frequency. Set the PhyControl0.ctrl_dll_on bit-field to ‘1’ to turn on the PHY DLL.
3. DQS Cleaning: Set the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetc bit-fields to correct value according to clock frequency and memory tAC parameters.
4. Set the PhyControl0.ctrl_start bit-field to ‘1’.
5. Set the ConControl. At this moment, an auto refresh counter should be off.
6. Set the MemControl. At this moment, all power down modes should be off.
7. Set the MemConfig0 register. If there are two external memory chips, set the MemConfig1 register.
8. Set the PrechConfig and PwrdnConfig registers.
9. Set the TimingAref, TimingRow, TimingData and TimingPower registers according to memory AC parameters.
10. If QoS scheme is required, set the QosControl0~15 and QosConfig0~15 registers.
11. Wait for the PhyStatus0.ctrl_locked bit-fields to change to ‘1’. Check whether PHY DLL is locked.
12. PHY DLL compensates the changes of delay amount caused by Process, Voltage and Temperature (PVT) variation during memory operation. Therefore, PHY DLL should not be off for reliable operation. It can be off except runs at low frequency. If off mode is used, set the PhyControl0.ctrl_force bit-field to correct value according to the PhyStatus0.ctrl_lock_value[9:2] bit-field to fix delay amount. Clear the PhyControl0.ctrl_dll_on bit-field to turn off PHY DLL.
13. Confirm whether stable clock is issued minimum 200us after power on
14. Issue a NOP command using the DirectCmd register to assert and to hold CKE to a logic high level.
15. Wait for minimum 400ns.
16. Issue a PALL command using the DirectCmd register.
17. Issue an EMRS2 command using the DirectCmd register to program the operating parameters.
18. Issue an EMRS3 command using the DirectCmd register to program the operating parameters.
19. Issue an EMRS command using the DirectCmd register to enable the memory DLLs.
20. Issue a MRS command using the DirectCmd register to reset the memory DLL.
21. Issue a PALL command using the DirectCmd register.
22. Issue two Auto Refresh commands using the DirectCmd register.
23. Issue a MRS command using the DirectCmd register to program the operating parameters without resetting the memory DLL.
24. Wait for minimum 200 clock cycles.
25. Issue an EMRS command using the DirectCmd register to program the operating parameters. If OCD calibration is not used, issue an EMRS command to set OCD Calibration Default. After that, issue an EMRS command to exit OCD Calibration Mode and to program the operating parameters.
26. If there are two external memory chips, perform steps 14~25 for chip1 memory device.
27. Set the ConControl to turn on an auto refresh counter. 28. If power down modes is required, set the MemControl registers.

自己逐条翻译并且按照其默认设置，初始化寄存器。

下面是我初始化的代码，如有问题可以讨论修改

#define MP1_0DRV (*(volatile unsigned long*)0xE02003CC)
#define MP1_1DRV (*(volatile unsigned long*)0xE02003EC)
#define MP1_2DRV (*(volatile unsigned long*)0xE020040C)
#define MP1_3DRV (*(volatile unsigned long*)0xE020042C)
#define MP1_4DRV (*(volatile unsigned long*)0xE020044C)
#define MP1_5DRV (*(volatile unsigned long*)0xE020046C)
#define MP1_6DRV (*(volatile unsigned long*)0xE020048C)
#define MP1_7DRV (*(volatile unsigned long*)0xE02004AC)
#define MP1_8DRV (*(volatile unsigned long*)0xE02004CC)


#define DMC0_PHYCONTROL0 (*(volatile unsigned long*)0xF0000018)
#define DMC0_PHYCONTROL1 (*(volatile unsigned long*)0xF000001C)
#define DMC0_PHYSTATUS0  (*(volatile unsigned long*)0xF0000040)


#define DMC0_CONCONTROL (*(volatile unsigned long*)0xF0000000)
#define DMC0_MEMCONTROL (*(volatile unsigned long*)0xF0000004)
#define DMC0_MEMCONFIG0 (*(volatile unsigned long*)0xF0000008)
#define DMC0_MEMCONFIG1 (*(volatile unsigned long*)0xF000000C)
#define DMC0_PRECHCONFIG (*(volatile unsigned long*)0xF0000014)
#define DMC0_PWRDNCONFIG (*(volatile unsigned long*)0xF0000028)
#define DMC0_TIMINGAREF (*(volatile unsigned long*)0xF0000030)
#define DMC0_TIMINGROW (*(volatile unsigned long*)0xF0000034)
#define DMC0_TIMINGDATA (*(volatile unsigned long*)0xF0000038)
#define DMC0_TIMINGPOWER (*(volatile unsigned long*)0xF000003C)
#define DMC0_DIRECTCMD (*(volatile unsigned long*)0xF0000010)
#define DMC0_PHYSTATUS (*(volatile unsigned long*)0xF0000040)


#define DMC1_PHYCONTROL0 (*(volatile unsigned long*)0xF1400018)
#define DMC1_PHYCONTROL1 (*(volatile unsigned long*)0xF140001C)
#define DMC1_PHYSTATUS0  (*(volatile unsigned long*)0xF1400040)


#define DMC1_CONCONTROL (*(volatile unsigned long*)0xF1400000)
#define DMC1_MEMCONTROL (*(volatile unsigned long*)0xF1400004)
#define DMC1_MEMCONFIG0 (*(volatile unsigned long*)0xF1400008)
#define DMC1_MEMCONFIG1 (*(volatile unsigned long*)0xF140000C)
#define DMC1_PRECHCONFIG (*(volatile unsigned long*)0xF1400014)
#define DMC1_PWRDNCONFIG (*(volatile unsigned long*)0xF1400028)
#define DMC1_TIMINGAREF (*(volatile unsigned long*)0xF1400030)
#define DMC1_TIMINGROW (*(volatile unsigned long*)0xF1400034)
#define DMC1_TIMINGDATA (*(volatile unsigned long*)0xF1400038)
#define DMC1_TIMINGPOWER (*(volatile unsigned long*)0xF140003C)
#define DMC1_DIRECTCMD (*(volatile unsigned long*)0xF1400010)
#define DMC1_PHYSTATUS (*(volatile unsigned long*)0xF1400040)


void ddr_init(){
MP1_0DRV = 0xAAAA;//DRAM驱动强度
MP1_1DRV = 0xAAAA;
MP1_2DRV = 0xAAAA;
MP1_3DRV = 0xAAAA;
MP1_4DRV = 0xAAAA;
MP1_5DRV = 0xAAAA;
MP1_6DRV = 0xAAAA;
MP1_7DRV = 0xAAAA;
MP1_8DRV = 0x2AAA；

DMC0_PHYCONTROL0 = 0x00101000;
DMC0_PHYCONTROL0 = 0x00101002;
DMC0_PHYCONTROL1 = 0x86;
DMC0_PHYCONTROL0 = 0x00101003;


while((DMC0_PHYSTATUS&0x7) != 0x7);


DMC0_CONCONTROL = 0x0FFF2010;
DMC0_MEMCONTROL = 0x00202400;
//DMC0_MEMCONFIG0 = 0x20E01323;
DMC0_MEMCONFIG1 = 0x40F01323;//有两片的设置1寄存器


DMC0_PRECHCONFIG = 0xFF000000;
DMC0_PWRDNCONFIG = 0xFFFF00FF;


DMC0_TIMINGAREF = 0x00000618;
DMC0_TIMINGROW = 0x28233287;
DMC0_TIMINGDATA = 0x23240304;
DMC0_TIMINGPOWER = 0x09C80232;
DMC0_PHYSTSTUS0 = 0x4;//11 PHY DLL is locked



DMC0_DIRECTCMD = 0x07000000;
DMC0_DIRECTCMD = 0x01000000;//所有板子预充电16
DMC0_DIRECTCMD = 0x00020000;
DMC0_DIRECTCMD = 0x00030000;
DMC0_DIRECTCMD = 0x00010400;
DMC0_DIRECTCMD = 0x00000542;
DMC0_DIRECTCMD = 0x01000000;//所有预充电21
DMC0_DIRECTCMD = 0x05000000;
DMC0_DIRECTCMD = 0x05000000;
DMC0_DIRECTCMD = 0x00000442;
DMC0_DIRECTCMD = 0x00010780;
DMC0_DIRECTCMD = 0x00010400;
DMC0_DIRECTCMD = 0x07100000;
DMC0_DIRECTCMD = 0x01100000;
DMC0_DIRECTCMD = 0x00120000;
DMC0_DIRECTCMD = 0x00130000;
DMC0_DIRECTCMD = 0x00110400;
DMC0_DIRECTCMD = 0x00100542;
DMC0_DIRECTCMD = 0x01100000;
DMC0_DIRECTCMD = 0x05100000;
DMC0_DIRECTCMD = 0x05100000;
DMC0_DIRECTCMD = 0x00100442;
DMC0_DIRECTCMD = 0x00110780;
DMC0_DIRECTCMD = 0x00110400;


DMC0_CONCONTROL = 0x0FF02030;
DMC0_PWRDNCONFIG = 0xFFFF00FF;
DMC0_MEMCONTROL = 0x00202400;


//DMC1
DMC1_PHYCONTROL0 = 0x00101000;
DMC1_PHYCONTROL0 = 0x00101002;
DMC1_PHYCONTROL1 = 0x86;
DMC1_PHYCONTROL0 = 0x00101003;


while((DMC0_PHYSTATUS&0x7) != 0x7);


DMC1_CONCONTROL = 0x0FFF2010;
DMC1_MEMCONTROL = 0x00202400;
DMC1_MEMCONFIG0 = 0x40E01323;
//DMC0_MEMCONFIG1 = 0x40F01323;


DMC1_PRECHCONFIG = 0xFF000000;
//DMC0_PWRDNCONFIG = 0xFFFF00FF;


DMC1_TIMINGAREF = 0x00000618;
DMC1_TIMINGROW = 0x28233287;
DMC1_TIMINGDATA = 0x23240304;
DMC1_TIMINGPOWER = 0x09C80232;





DMC1_DIRECTCMD = 0x07000000;
DMC1_DIRECTCMD = 0x01000000;
DMC1_DIRECTCMD = 0x00020000;
DMC1_DIRECTCMD = 0x00030000;
DMC1_DIRECTCMD = 0x00010400;
DMC1_DIRECTCMD = 0x00000542;
DMC1_DIRECTCMD = 0x01000000;
DMC1_DIRECTCMD = 0x05000000;
DMC1_DIRECTCMD = 0x05000000;
DMC1_DIRECTCMD = 0x00000442;
DMC1_DIRECTCMD = 0x00010780;
DMC1_DIRECTCMD = 0x00010400;
DMC1_DIRECTCMD = 0x07100000;
DMC1_DIRECTCMD = 0x01100000;
DMC1_DIRECTCMD = 0x00120000;
DMC1_DIRECTCMD = 0x00130000;
DMC1_DIRECTCMD = 0x00110400;
DMC1_DIRECTCMD = 0x00100542;
DMC1_DIRECTCMD = 0x01100000;
DMC1_DIRECTCMD = 0x05100000;
DMC1_DIRECTCMD = 0x05100000;
DMC1_DIRECTCMD = 0x00100442;
DMC1_DIRECTCMD = 0x00110780;
DMC1_DIRECTCMD = 0x00110400;


DMC1_CONCONTROL = 0x0FF02030;
DMC1_PWRDNCONFIG = 0xFFFF00FF;
DMC1_MEMCONTROL = 0x00202400;
}