spyglass 使用方法

//spyglass

//https://www.atrenta.com/

//templates

//Scripts

{//sg_designread

-top            :top-level design unit.

-sdcfile        :provide the name of design SDC file,

-activityfile   :provide the name of the activity file(VCD/FSDB) to be used for picking up the activity information for the design.

-bb             :provide the list of the design modules, which are explicitly be treated as blackboxes during SpyGlass analysis

-ip             :provide the list of 3rd party IPs, which are not be analyzed during SpyGlass analysis.

//run_spyglass

-top            :provide the name of the top-level design unit,comma separated multiple goal names,

-goals          :provide a goal nam

-show_goals     :to show the list of valid goal names,

-open_gui       :to load the spyglass goal results in SpyGlass GUI for debugging

}

 

//SpyGlass Flow

{//environment variable ‘SG_FLOW_PATH’ pointing ‘spyglass’ package

setenv SG_FLOW_PATH /home/proj1/tools/reference_flow 

1,  create a design source file ‘<module_name>.f’

2,  % sg_designread  -top=<module_name>

3,  % run_syglass   -top=<module_name> -goals=cdc_setup_check

4,  % run_spyglass –top=<module_name> -goals=<goal list>

}

//templates:

spyglass/sample_setup_files : This directory contains the reference templates for some of the setup files:

 

 

//waiver constrain:error or warning can be ignored

//file:默认生成：sg_setup/top/top.swl

//

{

e.g: waive -file "/home/apps/rtl/abc.v"

e.g: waive -regexp -file "/home/apps/rtl/abc.*" //带正则表达式的文件

e.g: waive -du "apb_sci_top" //module name，

e.g: waive -regexp -du "apb_sci_*"

e.g: waive -ip "apb_sci_top" //module name、Ip的名字，

e.g: waive -rule "W164a" //rule name

 

}

 

//spyglass design constrain file

//file:默认生成：sg_setup/top/top.sgdc

{

 

}

 

//spyglass goals

//>% run_spyglass –top=top –goals=lint_basic,cdc_structural_check

{

audit : e.g. gatecount, instancecount, flop count, design hierarchy and tree, probable clock & reset signals etc, about the design.  

lint

    lint_basic      : related to connectivity, simulation-synthesis mismatches, synthesis readiness, re-usability etc  

    lint_optional   : Checks the RTL design for additional less critical lint checks  

cdc 

    cdc_setup_check :Checks the completeness of clock & reset constraints setup. clock, reset, set_case_analysis 

    cdc_structural_check    : all clock domain crossing paths and reset synchronization. clock, reset, set_case_analysis, cdc_false_path 

    cdc_functional_check    : Checks the functional correctness(data loss etc) of CDC paths (using formal verification engine)  clock,reset, set_case_analysis, cdc_false_path 

dft_check Checks ready for scan insertion and also identifies the testability issue and ATPG bottlenecks clock -testclock, testmode, scan_wrap 

power 

    power_audit Perform audit check on data inputs needed for power estimation Activity MUST

    power_est_average Estimates the average power of the design. activity_data, select_wireload_model MUST

}

 

{//create new file sg.setup

define environment variable:

setenv CBB_RTL_DIR /home/apps/rtl/abc/

}

 

{//create new file <top>.f

-f abc.f

-f efg.f ...

}