Rockchip 3288 DDR单通道支持补丁

From ce0ea7ca53788696a59e882dc48df119b5315282 Mon Sep 17 00:00:00 2001
From: Hecanyang <hcy@rock-chips.com>
Date: Thu, 8 Jun 2017 21:19:02 +0800
Subject: [PATCH] arm: rk3288: ddr: pm: fix only one ddr channel's bug

The system pm suspend will crash when only use one ddr channel.
this commit need to match up uboot's
commit ddr: ddr update to 20151202 version
("5d9f2dc3808eb54d71ce3ea0662acc94491f48a1")
that can support use only one ddr channel.

Change-Id: I1cac03f0b98e0ee25ca89c4267266b5888a6e6d9
Signed-off-by: Hecanyang <hcy@rock-chips.com>
---
 arch/arm/mach-rockchip/ddr_rk32.c  | 12 ++----
 arch/arm/mach-rockchip/pm-rk3288.c | 87 +++++++++++++++++++++++++++-----------
 2 files changed, 66 insertions(+), 33 deletions(-)

diff --git a/arch/arm/mach-rockchip/ddr_rk32.c b/arch/arm/mach-rockchip/ddr_rk32.c
index f661005..0aa1290 100644
--- a/arch/arm/mach-rockchip/ddr_rk32.c
+++ b/arch/arm/mach-rockchip/ddr_rk32.c
@@ -4248,24 +4248,22 @@ void ddr_reg_save(uint32 *pArg)
     pMSCH_REG     pMSCH_Reg;
     
     p_ddr_reg->tag = 0x56313031;
+    p_ddr_reg->pctlAddr[0] = RK3288_DDR_PCTL0_PHYS;
+    p_ddr_reg->publAddr[0] = RK3288_DDR_PUBL0_PHYS;
     if(p_ddr_ch[0]->mem_type != DRAM_MAX)
     {
-        p_ddr_reg->pctlAddr[0] = RK3288_DDR_PCTL0_PHYS;
-        p_ddr_reg->publAddr[0] = RK3288_DDR_PUBL0_PHYS;
         p_ddr_reg->nocAddr[0] = RK3288_SERVICE_BUS_PHYS;
         pDDR_Reg = p_ddr_ch[0]->pDDR_Reg;
         pPHY_Reg = p_ddr_ch[0]->pPHY_Reg;
     }
     else
     {
-        p_ddr_reg->pctlAddr[0] = 0xFFFFFFFF;
-        p_ddr_reg->publAddr[0] = 0xFFFFFFFF;
         p_ddr_reg->nocAddr[0] = 0xFFFFFFFF;
     }
+    p_ddr_reg->pctlAddr[1] = RK3288_DDR_PCTL1_PHYS;
+    p_ddr_reg->publAddr[1] = RK3288_DDR_PUBL1_PHYS;
     if(p_ddr_ch[1]->mem_type != DRAM_MAX)
     {
-        p_ddr_reg->pctlAddr[1] = RK3288_DDR_PCTL1_PHYS;
-        p_ddr_reg->publAddr[1] = RK3288_DDR_PUBL1_PHYS;
         p_ddr_reg->nocAddr[1] = RK3288_SERVICE_BUS_PHYS+0x80;
         if((pDDR_Reg == NULL) || (pPHY_Reg == NULL))
         {
@@ -4275,8 +4273,6 @@ void ddr_reg_save(uint32 *pArg)
     }
     else
     {
-        p_ddr_reg->pctlAddr[1] = 0xFFFFFFFF;
-        p_ddr_reg->publAddr[1] = 0xFFFFFFFF;
         p_ddr_reg->nocAddr[1] = 0xFFFFFFFF;
     }
     
diff --git a/arch/arm/mach-rockchip/pm-rk3288.c b/arch/arm/mach-rockchip/pm-rk3288.c
index 3573e7b..a122b48 100755
--- a/arch/arm/mach-rockchip/pm-rk3288.c
+++ b/arch/arm/mach-rockchip/pm-rk3288.c
@@ -969,13 +969,32 @@ static u32  rkpm_slp_mode_set(u32 ctrbits)
     else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMOFF_LPMD))
     {   
         rkpm_ddr_printascii("-armoff-");                         
-        mode_set|=BIT(pmu_scu_en)
-                            //|BIT(pmu_a12_0_pd_en) 
-                            |BIT(pmu_clk_core_src_gate_en) // 唤醒后异常
-                            |BIT(pmu_sref0_enter_en)|BIT(pmu_sref1_enter_en) 
-                            |BIT(pmu_ddr0_gating_en)|BIT(pmu_ddr1_gating_en)              
-                            //|BIT(pmu_ddr1io_ret_en)|BIT(pmu_ddr0io_ret_en)   
-                            |BIT(pmu_chip_pd_en);
+    if ((pmu_readl(RK3288_PMU_SYS_REG2) >> 12) & 1)
+        mode_set |= BIT(pmu_scu_en)
+            //|BIT(pmu_a12_0_pd_en)
+            | BIT(pmu_clk_core_src_gate_en)
+            | BIT(pmu_sref0_enter_en)
+            | BIT(pmu_sref1_enter_en)
+            | BIT(pmu_ddr0_gating_en)
+            | BIT(pmu_ddr1_gating_en)
+            //|BIT(pmu_ddr1io_ret_en)|BIT(pmu_ddr0io_ret_en)
+            | BIT(pmu_chip_pd_en);
+    else
+        /*
+         * remove BIT(pmu_sref1_enter_en)
+         * BIT(pmu_ddr1_gating_en)
+         * when there's only one ddr channel
+         */
+        mode_set |= BIT(pmu_scu_en)
+            //|BIT(pmu_a12_0_pd_en)
+            | BIT(pmu_clk_core_src_gate_en)
+            | BIT(pmu_sref0_enter_en)
+            /* |BIT(pmu_sref1_enter_en) */
+            | BIT(pmu_ddr0_gating_en)
+            /* |BIT(pmu_ddr1_gating_en) */
+            /* |BIT(pmu_ddr1io_ret_en) */
+            /* |BIT(pmu_ddr0io_ret_en) */
+            | BIT(pmu_chip_pd_en);
         mode_set1=BIT(pmu_clr_core)|BIT(pmu_clr_cpup)
                                 |BIT(pmu_clr_alive)
                                 |BIT(pmu_clr_peri)
@@ -985,16 +1004,35 @@ static u32  rkpm_slp_mode_set(u32 ctrbits)
     } 
     else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMOFF_LOGDP_LPMD))
     {
-    
-        rkpm_ddr_printascii("-armoff-logdp-");        
-        
-        mode_set|=BIT(pmu_scu_en)|BIT(pmu_bus_pd_en)
-                            |BIT(pmu_chip_pd_en)
-                            |BIT(pmu_sref0_enter_en)|BIT(pmu_sref1_enter_en) 
-                            |BIT(pmu_ddr0_gating_en)|BIT(pmu_ddr1_gating_en)              
-                            |BIT(pmu_ddr1io_ret_en)|BIT(pmu_ddr0io_ret_en)   
-                            |BIT(pmu_osc_24m_dis)|BIT(pmu_pmu_use_lf)|BIT(pmu_alive_use_lf)|BIT(pmu_pll_pd_en)
-                            ;
+    rkpm_ddr_printascii("-armoff-logdp-");
+
+    if ((pmu_readl(RK3288_PMU_SYS_REG2) >> 12) & 1)
+        mode_set |= BIT(pmu_scu_en) | BIT(pmu_bus_pd_en)
+            | BIT(pmu_chip_pd_en)
+            | BIT(pmu_sref0_enter_en) | BIT(pmu_sref1_enter_en)
+            | BIT(pmu_ddr0_gating_en) | BIT(pmu_ddr1_gating_en)
+            | BIT(pmu_ddr0io_ret_en) | BIT(pmu_ddr1io_ret_en)
+            | BIT(pmu_osc_24m_dis) | BIT(pmu_pmu_use_lf)
+            | BIT(pmu_alive_use_lf) | BIT(pmu_pll_pd_en)
+            ;
+    else
+        /*
+         * remove BIT(pmu_sref1_enter_en)
+         * BIT(pmu_ddr1_gating_en)
+         * BIT(pmu_ddr1io_ret_en)
+         * when there's only one ddr channel
+         */
+        mode_set |= BIT(pmu_scu_en) | BIT(pmu_bus_pd_en)
+            | BIT(pmu_chip_pd_en)
+            | BIT(pmu_sref0_enter_en)
+            /* |BIT(pmu_sref1_enter_en) */
+            | BIT(pmu_ddr0_gating_en)
+            /* |BIT(pmu_ddr1_gating_en) */
+            /* |BIT(pmu_ddr1io_ret_en) */
+            | BIT(pmu_ddr0io_ret_en)
+            | BIT(pmu_osc_24m_dis) | BIT(pmu_pmu_use_lf)
+            | BIT(pmu_alive_use_lf) | BIT(pmu_pll_pd_en)
+            ;
         mode_set1=BIT(pmu_clr_core)|BIT(pmu_clr_cpup)
                            |BIT(pmu_clr_alive)
                            |BIT(pmu_clr_peri)
@@ -1861,14 +1899,13 @@ static void gpio_get_dts_info(struct device_node *parent)
         if(temp_len)
         {
             printk("%s suspend:%d\n",__FUNCTION__,temp_len);
-            if(temp_len)
-            {
-                if(of_property_read_u32_array(parent,"rockchip,pmic-suspend_gpios",&suspend_gpios[0],temp_len/4))
-                {
-                        suspend_gpios[0]=0;
-                       printk("%s:get pm ctr error\n",__FUNCTION__);
-                }
-            }
+        if (of_property_read_u32_array(parent,
+                          "rockchip,pmic-suspend_gpios",
+                          &suspend_gpios[0],
+                          temp_len / 4)) {
+            suspend_gpios[0] = 0;
+            pr_err("%s:get pm ctr error\n", __func__);
+        }
         }
 
        temp_len=of_find_property_value_getsize(parent,"rockchip,pmic-resume_gpios");
-- 
2.0.0