//XW_
crc_p.v `pragma protect begin module DW_
crc_p( data_in,
crc_in,
crc_ok,
crc_out ); parameter integer data_width = 16; parameter integer poly_size = 16; parameter integer
crc_cfg = 7; parameter integer bit_order = 3; parameter integer poly_coef0 = 4129; parameter integer poly_coef1 = 0; parameter integer poly_coef2 = 0; parameter integer poly_coef3 = 0; input [data_width-1:0] data_in; input [poly_size-1:0]
crc_in; output
crc_ok; output [poly_size-1:0]
crc_out; `define DW_max_data_
crc_1 (data_width>poly_size?data_width:poly_size) wire [poly_size-1:0]
crc_in_inv; wire [poly_size-1:0]
crc_reg; wire [poly_size-1:0]
crc_out_inv; wire [poly_size-1:0]
crc_chk_
crc_in; reg [poly_size-1:0]
crc_inv_alt; reg [poly_size-1:0]
crc_polynomial; `include "bit_order_
crc_function.inc" `include "bit_order_data_function.inc" `include "calculate_
crc_w_in_function.inc" `include "calculate_
crc_function.inc" `include "calculate_
crc_
crc_function.inc" generate //begin genvar bit_idx; reg [63:0]
crc_polynomial64; reg [15:0] coef0; reg [15:0] coef1; reg [15:0] coef2; reg [15:0] coef3; assign coef0= poly_coef0; assign coef0= poly_coef1; assign coef0= poly_coef2; assign coef0= poly_coef3; assign
crc_polynomial64 = {coef3, coef2, coef1, coef0}; assign
crc_pollynomial =
crc_polynomial64[poly_size-1:0]; case(
crc_cfg/2) 0: assign
crc_inv_alt = {poly_size{1'b0}}; 1: for(bit_idx = 0; bit_idx<poly_sizel bit_idx=bit_idx+1) assign
crc_inv_alt[bit_idx] = (bit_idx % 2)? 1'b0:1'b1; 2: for(bit_idx=0; bit_idx<poly_size; bit_idx=bit_idx+1) assign
crc_inv_alt[bit_idx] = (bit_idx % 2)?1'b1:1'b0; 3: assign
crc_inv_alt = { poly_size{1'b1}}; endcase endgenerate assign
crc_in_inv = bit_order_
crc(
crc_in) ^
crc_inv_alt; assign
crc_reg = calculate_
crc(bit_order_data(data_in)); assign
crc_out_inv =
crc_reg; assign
crc_out = bit_order_
crc(
crc_out_inv)^
crc_inv_alt; assign
crc_chk_
crc_in = calculate_
crc_
crc(
crc_reg,
crc_in_inv); assign
crc_ok = (
crc_chk_
crc_in ==0); `undef DW_max_data_
crc_1 endmodule `pragma protect end can you write a testbench for this piece of
CRC verilog code so that this verilog file and the testbench can be used togerther by vcs to verify the correctness of this verilog file?
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