s5pv210 datasheet_system_clock controler

3 CLOCK CONTROLLER
This chapter describes the clock management unit (CMU) supported by S5PV210. The system controller
(SYSCON) manages CMU and power management unit (PMU) in S5PV210.
3.1 CLOCK DOMAINS
S5PV210 consists of three clock domains, namely, main system (MSYS),display system (DSYS), and peripheral
system (PSYS), as shown in Figure 3-1.
• MSYS domain comprises Cortex A8 processor, DRAM memory controllers (DMC0 and DMC1), 3D, internal
SRAM (IRAM, and IROM), INTC, and configuration interface (SPERI). Cortex A8 supports only synchronous
mode, and therefore it must operate synchronously with 200MHz AXI buses.
• DSYS domain comprises display related modules, including FIMC, FIMD, JPEG, and multimedia IPs (all other
IPs mentioned in X, L, and T blocks), as shown in Figure 3-1.
• PSYS domain is used for security, I/O peripherals, and low power audio play.
• Each bus system operates at 200 MHz (maximum), 166 MHz, and 133 MHz, respectively. There are

asynchronous bus bridges (BRG) between two different domains.   

3.4 CLOCK GENERATION
Figure 3-3 shows block diagram of the clock generation logic. An external crystal clock is connected to the
oscillation amplifier. The PLL converts low input frequency to high-frequency clock required by S5PV210. The
clock generator block also includes a built-in logic to stabilize the clock frequency after each system reset, since
clock takes time before stabilizing.

图3-3显示时钟生成逻辑框图。一个外部的晶体时钟被连接到振荡放大器。PLL将低输入频率转换到S5PV210所需的高频时钟。

这个时钟发生器块还包括一个内置的逻辑，以稳定的时钟频率后，每个系统复位，因为在稳定之前，时钟需要时间。

Figure 3-3 also shows two types of clock mux. Clock mux in grey color represents glitch-free clock mux, which is
free of glitches if clock selection is changed. Clock mux in white color represents non-glitch-free clock mux, which
can suffer from glitches when changing clock sources. Care must be taken in using each of clock muxes. For
glitch-free mux, it should be guaranteed that both of clock sources are running when clock selection is changed
from one to the other. 

图3-3显示两种时钟选择。在灰色的时钟选择代表无毛刺时钟多路复用器，它是无毛刺，如果时钟选择改变。白色时钟MUX代表非无毛刺时钟多路复用器，

当更换时钟源它能承受故障。必须使用每个时钟复用器了。对于无毛刺复用，就必须保证两时钟源运行时的时钟选择从一个改变到另一个。

If that's not the case, clock changing is not finished fully and resulting clock output can have
unknown states. For non-glitch-free clock mux, it is possible to have a glitch when clock selections are changed.
To prevent the glitch signals, it is recommended to disable output of non-glitch-free muxes before trying to change
clock sources. After clock changing is completed, users can re-enable output of the non-glitch-free clock mux so
that there will be no glitches resulting from clock changes. Masking output of non-glitch-free muxes are handled by
clock source control registers.

如果不是这样的话，时钟的变化是没有完成充分，并由此产生的时钟输出可能是未知的状态。

非无毛刺时钟多路复用器，它可能有一个故障时改变时钟选择。

为防止干扰信号，建议在试图改变禁用非无毛刺器输出时钟源。

在时钟的改变完成后，用户可以重新启用非无毛刺时钟MUX输出将无毛刺时钟产生的变化。

屏蔽非无毛刺器输出由时钟源控制寄存器处理。

Clock dividers shown in Figure 3-3 indicates possible dividing value in parentheses. Those diving values can be
decided by clock divider registers on run-time. Some clock dividers can only have one dividing value and user
cannot change them and does not have corresponding fields in clock divider registers.

时钟分频器图3-3所示表明括号中可能的分界值。这些分频值可以由时钟分频器在运行时决定。一些时钟分频器只能有一个分频值同时用户不能改变它们，

并且没有相应的字段在时钟分频器寄存器。