s5pv210 datasheet_system_memory

最新推荐文章于 2016-05-18 08:46:53 发布

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最新推荐文章于 2016-05-18 08:46:53 发布

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1 DRAM CONTROLLER
1.1 OVERVIEW OF DRAM CONTROLLER
1.1.1 INTRODUCTION OF DRAM CONTROLLER
The DRAM controller is an Advanced Microcontroller Bus Architecture (AMBAtm) AXI compliant slave to interface
external JEDEC DDR-type SDRAM devices.
To support high-speed memory devices, the DRAM controller uses a SEC DDR PHY interface. The controller
includes an advanced embedded scheduler toutilize memory device efficiently and an optimized pipeline stage to
minimize latency. S5PV210 has two independent DRAM Controllers and Ports, namely, DMC0 and DMC1. DMC0
support maximum 512MByte and DMC1 1GByte memory size but both controllers must use the memory of the

same type.

DRAM控制器是一种先进的微控制器总线架构（ambatm）AXI兼容接口的从设备连接到JEDEC DDR SDRAM外部类型器件。

支持高速内存、DRAM控制器使用一秒的DDR PHY接口。

控制器包括一个先进的嵌入式调度程序，以有效地利用内存设备和优化的流水线阶段

最小化等待时间。S5PV210有两个独立的DRAM控制器和端口，即DMC0和DMC1。dmc0

支持的最大内存大小和DMC1 512Mbyte 1GByte但控制器必须使用同类型的内存。

1.1.2 KEY FEATURES OF DRAM CONTROLLER
• Compatible with JEDEC DDR2, low power DDR and low power DDR2 SDRAM specification
• Uses the SEC LPDDR2 PHY interface to support high-speed memory devices
• Supports up to two external chip selects and 1/2/4/8 banks per one chip
• Supports 128 Mb, 256 Mb, 512 Mb, 1 Gb, 2 Gb and 4 Gb density Memory Devices
• Supports 16/ 32-bit wide memory data width
• Optimized pipeline stage for low latency
• Supports QoS scheme to ensure low latency for some applications
• Advanced embedded scheduler enables out-of order operations to utilize memory device efficiently
• Supports excellent chip/bank interleaving and memory interrupting
• Supports AMBA AXI low power channel for systematic power control
• Adapts to various low power schemes to reduce the dynamic and static current of memory
• Supports outstanding exclusive accesses
• Supports bank selective precharge policy

DRAM控制器的主要特点

•兼容JEDEC DDR2的低功耗DDR和DDR2 SDRAM规范低功率

•采用SEC LPDDR2 PHY接口支持高速存储设备

•支持多达2个外部芯片的选择和1 / 2 / 4 / 8家银行的每一个芯片

•支持128 MB，256 MB，512 MB，1 GB，2 GB和4 GB密度存储设备

•支持16 / 32位宽内存数据宽度

•为低延迟优化管道阶段

•支持服务质量计划，以确保某些应用程序的低延迟

•高级嵌入式调度器使能有效地利用存储设备的订单操作

•支持优秀的芯片/bank交织和内存中断

•支持AMBA AXI的低功率信道系统的功率控制

•适应各种低功耗方案，以减少内存的动态和静态内存

•支持出色的独家访问

•支持银行选择性预充电策略

1.2.2 ADDRESS MAPPING
The controller modifies the address of the bus transaction coming from the AXI slave port into a memory address -
chip select, bank address, row address, column address and memory data width.

1.2.2地址映射

控制器的总线事务修改地址来自传输从端口到一个内存地址—芯片选择，bank地址，行地址，列地址和内存数据宽度。

To map chip select0 of the memory device to a specific area of the address map, thechip_base andchip_mask
bit-fields of the MemConfig0register must be set (Refer to Register Descriptions). If chip1 of the memory device
exists, the MemConfig1register must also be set.

映射内存的装置的一个特定区域的地址映射芯片的select0，chip_base和chip_mask

memconfig0登记的位域必须设置（指登记说明）。如果存储器芯片存在的memconfig1登记也必须设置。

Then, the AXI address requested by the AXI Master is divided into AXI base address and AXI offset address.
The AXI base address activates the appropriate memory chip select and the AXI offset address is mapped to a
memory address according to the bank, row, column number, and data width set by theMemConfig register.
There are two ways to map the AXI offset address as shown inFigure 1-2 Linear mapping and Interleaved
mapping.