各种接口在高速PCB中的应用（基于RK系列，最全最完整）

Depending on the type of interface, there are different layout requirements available. This section provides an overview of the major interfaces.

The differential pair signals normally distinguish between two different length matching requirements. The first requirement is the maximum intra-pair skew. This is the maximum allowed length differences between the positive and negative signal of the pairs. As described in section , not only should the overall length be matched, but also the length within a section of the signal should be corrected. It is important that the positive and negative signal components are propagated synchronously. Only if these signals are synchronous, their fields are compensated and the electromagnetic radiation is reduced.

The second length matching requirement is the maximum allowed skew between the clock and signal pairs or between different pairs of the same interface. Some of the interfaces (e.g. PCIe, EDP, DP,and USB3.0) are recovering the clock signal out of the data signals. Therefore, the matching between the clock and data signals can be quite relaxed. Do not try to overmatch such interfaces since it is really not required and the additional meander just introduces other signal quality problems. On the other hand there are interfaces which do not have an embedded clock signal (e.g. Mipi interface). Please route these signals very carefully. The length matching between the clock and data signals needs to be met.

Vias introduce a major discontinuity of the impedance and can create signal stubs. Therefore, the amount of vias should be kept as low as possible.

PCI Express

Parameter	Requirement
Trace Impedance	100Ω ±10% differential
Max intra-pair skew	<4ps
Max inter-pair skew	<1.6ns
Maximum signal line length (coupled traces) TX and RX	<14 inches
AC coupling capacitors	100nF ±20%, discrete 0201 package preferable
Minimum pair to pair spacing	>3 times the width of the trace.Try to increase Spacing between pairs whenever it is possible.
Length matching between reference clock differential pairs REFCLK+ and REFCLK- (intra-pair)	<4ps
The minimum spacing between PCIE and other Signals	At least 3 times the width of PCIE trace.
Maximum allowed via	4

Note:
It is suggest that PCIE signals route together .Don’t have any other signals and via within PCIE signals .

USB

The layout requirement for USB interfaces depends on the version that needs to be supported. Up to USB 2.0, the interface was consisting of a single bidirectional data signal pair. The USB 3.0 standard introduces two additional data signal pairs for the Super Speed link. These two pairs are running at 5 Gbit/s .

Parameter	Requirement
Trace Impedance	90Ω ±10% differential
Max intra-pair skew	<4ps
Max trace length on carrier board	<6 inches
Maximum allowed via	6

USB 3.0 Signals

Parameter	Requirement
Max intra-pair skew	90Ω ±10% differential
Max intra-pair skew	<4ps
Max trace length skew between RX and TX data pairs	<1.6ns
Max trace length on carrier board	<6 inches
AC coupling capacitors	100nF ±20%, discrete 0201 package preferable
Minimum pair to pair spacing	>3 times the width of the trace.Try to increase Spacing between pairs whenever it is possible.
Length matching between reference clock differential pairs REFCLK+ and REFCLK- (intra-pair)	<4ps
The minimum spacing between USB and other Signals	At least 3 times the width of USB trace.
Maximum allowed via	4

Note:
It is suggest that USB signals route together .Don’t have any other signals and via within USB signals .

HDMI

Parameter	Requirement
Trace Impedance	100Ω ±10% differential
Max intra-pair skew	<4ps
Max trace length skew between clock and data pairs	<80ps
Max trace length on carrier board	<9.8 inches
Minimum pair to pair spacing	>3 times the width of the trace.Try to increase Spacing between pairs whenever it is possible.
The minimum spacing between HDMI and other Signals	At least 3 times the width of HDMI trace.
Maximum allowed via	4

Note:
It is suggest that HDMI signals route together .Don’t have any other signals and via within HDMI signals .

EDP

Parameter	Requirement
Trace Impedance	90Ω ±10% differential
Max intra-pair skew	<4ps
Max trace length on carrier board	<6 inches
Minimum pair to pair spacing	>3 times the width of the trace.Try to increase Spacing between pairs whenever it is possible.
AC coupling capacitors	100nF ±20%, discrete 0201 package preferable
The minimum spacing between EDP and other Signals	At least 3 times the width of EDP trace.
Maximum allowed via	4

Note:
It is suggest that EDP signals route together .Don’t have any other signals and via within EDP signals .

Display Port

Parameter	Requirement
Trace Impedance	90Ω ±10% differential
Max intra-pair skew	<4ps
Maximum signal line length (coupled traces)	<6 inches
Minimum pair to pair spacing	>3 times the width of the trace.Try to increase Spacing between pairs whenever it is possible.
AC coupling capacitors	100nF ±20%, discrete 0201 package preferable
The minimum spacing between Display Port and other Signals	At least 3 times the width of Display Port trace.
Maximum allowed via	4

Note:
It is suggest that Display Port signals route together .Don’t have any other signals and via within Display Port signals .

Mipi

Parameter	Requirement
Trace Impedance	100Ω ±10% differential
Max intra-pair skew	<4ps
Max trace length skew between clock and data pairs	<7ps
Max trace length	<7.2 inches
Maximum allowed via	Minimize the number of via in each lane
Minimum pair to pair spacing	>3 times the width of the trace.Try to increase Spacing between pairs whenever it is possible.
The minimum spacing between Mipi and other Signals	At least 3 times the width of Mipi trace.

Note:
It is suggest that Mipi signals route together .Don’t have any other signals and via within Mipi signals .

EMMC

EMMC V5.0/V5.1

Parameter	Requirement
Trace Impedance	50Ω ±10% single ended
Max skew between data signal and clock	<20ps
Max trace length	< 3.93 inches
The minimum spacing of EMMC Signals	At least 2 times the width of EMMC trace.
The minimum spacing between EMMC and other Signals	At least 3 times the width of EMMC trace.

Note:
It is suggest that EMMC signals route together .Don’t have any other signals and via within EMMC signals .

SPI

Parameter	Requirement
Trace Impedance	50Ω ±10% single ended
Max skew between data signal and clock	<100ps
Max trace length	<5 inches

UART

Parameter	Requirement
Trace Impedance	50Ω ±10% single ended
Max skew between data signals	<100ps
Max trace length	<5 inches

SDIO

Parameter	Requirement
Trace Impedance	50Ω ±10% single ended
Max skew between data signal and clock	<20ps
Max trace length	< 3.93 inches
The minimum spacing of SDIO Signals	At least 2 times the width of SDIO trace.

USIC

Parameter	Requirement
Trace Impedance	50Ω ±10% single ended
Max skew between USIC_DATA and USIC_STROBE	<5ps
Max trace length	< 3.93 inches
USIC_DATA and USIC_STROBE Spacing	≥3 times the width of the trace