USB主机控制器(Host Controller)--深入理解

转自:https://blog.csdn.net/MyArrow/article/details/8500155

一、 主机控制器(Host Controller)

1.1 主机控制器简介

UHCI: Universal Host Controller Interface (通用主机控制接口, USB1.0/1.1)
OHCI: Open Host Controller Interface (开放主机控制接口,USB1.0/1.1)
EHCI: Enhanced Host Controller Interface (用于USB2.0高速设备的“增强主机控制接口”)

   USB的拓扑结构决定了主机控制器就是最高统帅,没有主机控制器的要求设备永远不能主动发数据。所以主机控制器在USB的世界里扮演着重要的角色,它是幕后操纵者。

问题:比如说Host发送Setup包获取设备描述符是怎么发出去的?

  这个过程包含很多信息,比如:如何在D+和D-这两根线上传过去的、又传过来的。 这一切的工作都是主机控制器给我们做的。USB Host控制器的规范有很多种,这里只介绍混得不错的EHCI和OHCI。这个EHCI主要针对高速的USB设备。如果要操作全速和低速可以考虑OHCI。

问题:什么是USB controller?

  USB 设备和主机的接口就是host controller,一个主机可以支持多个host controller,比如分别属于不同厂商的。USB host controller的作用:控制所有的USB设备的通信。

  CPU把要做的事情分配给主机控制器,然后自己想干什么就干什么去,主机控制器替他去完成剩下的事情,事情办完了再通知CPU。否则让CPU去盯着每一个设备做每一件事情,那是不现实的。

  控制器的主要工作是什么? 把数扔出去,把数拿回来。绝对不应该偷偷加工数据。

  主机控制器控制总线上包的传输, 使用1ms或125us的帧。在每帧的开始时,主机控制器产生一个帧开始包(SOF: Start of Frame)。

  SOF包用于同步帧的开始和跟踪帧的数目。包在帧中被传输,或由Host到Device(out事务),或由Device到Host(in事务)。传输总是由Host发起(轮询传输)。回此每条USB总线只能有一个Host。每个包的传输都有一个状态阶段同(同步传输除外),数据接收者可以在其中返回ACK(应答接收),NAK(重试),STALL(错误条件)或什么也没有(混乱数据阶段,设备不可用或已经断开)。

问题: 主机控制器Driver的工作是什么?

  让主机控制器工作起来,发挥它的潜力。 让控制器发数据、收数据 。主机控制器主要包含以下几步:

  1. 按照主机控制器的要求组织结构体
  2. 将结构体在合适的时间、放在合适的地方
  3. trigger
  4. 等待完成信号
    主机控制器Driver开发过程就是上面这几步。

二、 关键数据结构

  关键数据结构关系如下图所示:
在这里插入图片描述

三、系统架构

在这里插入图片描述
  EHCI负责处理高速设备,OHCI负责处理全速/低速设备。上面这张图描述了USB控制器在route USB设备时的操作。
  一个port 多个主人,OHCI的角色是companion,伴侣。地位低点。EHCI处理不了再给它处理。
在这里插入图片描述
  关于端口逻辑这块需要特别注意,Driver设计者要注意:当前端口正在属于谁。当端口被OHCI所拥有时,你插入个高速设备怎么办?没办法!在没有插入设备时,就不应该让OHCI拥有这个端口。只有EHCI控制器才能识别出设备是全速、高速还是低速。

四、 usb_submit_urb

  usb_submit_urb处理流程如下图所示:
在这里插入图片描述

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TABLE OF CONTENTS<br>1. INTRODUCTION.........................................................................................................1<br>2. TERMS AND ABBREVIATIONS.................................................................................2<br>3. ARCHITECTURAL OVERVIEW..................................................................................6<br>3.1 Introduction..........................................................................................................6<br>3.2 Data Transfer Types............................................................................................7<br>3.3 Host Controller Interface.....................................................................................7<br>3.3.1 Communication Channels............................................................................................7<br>3.3.2 Data Structures...........................................................................................................8<br>3.4 Host Controller Driver Responsibilities...........................................................12<br>3.4.1 Host Controller Management....................................................................................12<br>3.4.2 Bandwidth Allocation................................................................................................12<br>3.4.3 List Management......................................................................................................13<br>3.4.4 Root Hub..................................................................................................................13<br>3.5 Host Controller Responsibilities......................................................................13<br>3.5.1 USB States...............................................................................................................13<br>3.5.2 Frame management...................................................................................................14<br>3.5.3 List Processing..........................................................................................................14<br>4. DATA STRUCTURES...............................................................................................15<br>4.1 Overview.............................................................................................................15<br>4.2 Endpoint Descriptor..........................................................................................16<br>4.2.1 Endpoint Descriptor Format......................................................................................16<br>4.2.2 Endpoint Descriptor Field Definitions........................................................................17<br>4.2.3 Endpoint Descriptor Description...............................................................................18<br>4.3 Transfer Descriptors.........................................................................................19<br>4.3.1 General Transfer Descriptor......................................................................................19<br>4.3.1.1 General Transfer Descriptor Format...................................................................20<br>4.3.1.2 General Transfer Descriptor Field Definitions.....................................................20<br>4.3.1.3 General Transfer Descriptor Description.............................................................21<br>4.3.1.3.1 Buffer Address Determination.....................................................................21<br>4.3.1.3.2 Packet Size..................................................................................................21<br>4.3.1.3.3 Condition Codes..........................................................................................22<br>4.3.1.3.4 Sequence Bits..............................................................................................22<br>4.3.1.3.5 Transfer Completion....................................................................................23<br>4.3.1.3.6 Transfer Errors............................................................................................23<br>4.3.1.3.6.1 Transmission Errors..............................................................................24<br>4.3.1.3.6.2 Sequence Errors...................................................................................24<br>vi<br><br>OpenHCI - Open Host Controller Interface Specification for USB<br>4.3.1.3.6.3 System Errors.......................................................................................25<br>4.3.1.3.7 Special Handling..........................................................................................25<br>4.3.1.3.7.1 NAK.....................................................................................................25<br>4.3.1.3.7.2 Stall......................................................................................................25<br>4.3.2 Isochronous Transfer Descriptor...............................................................................25<br>4.3.2.1 Isochronous Transfer Descriptor Format............................................................25<br>4.3.2.2 Isochronous Transfer Descriptor Field Definitions..............................................26<br>4.3.2.3 Isochronous Transfer Descriptor Description......................................................26<br>4.3.2.3.1 Buffer Addressing........................................................................................27<br>4.3.2.3.2 Data Packet Size.........................................................................................28<br>4.3.2.3.3 Status..........................................................................................................28<br>4.3.2.3.4 Transfer Completion....................................................................................28<br>4.3.2.3.5 Transfer Errors............................................................................................28<br>4.3.2.3.5.1 Transmission Errors..............................................................................29<br>4.3.2.3.5.2 Sequence Errors...................................................................................29<br>4.3.2.3.5.3 Time Errors..........................................................................................29<br>4.3.2.3.5.4 System Errors.......................................................................................30<br>4.3.2.3.6 Special Handling..........................................................................................31<br>4.3.2.3.6.1 NAK and STALL.................................................................................31<br>4.3.2.4 PacketStatusWord..............................................................................................31<br>4.3.2.4.1 Packet Status Word Field Definitions...........................................................31<br>4.3.3 Completion Codes.....................................................................................................32<br>4.3.3.1 Condition Code Description...............................................................................33<br>4.4 Host Controller Communications Area............................................................33<br>4.4.1 Host Controller Communications Area Format..........................................................34<br>4.4.2 Host Controller Communications Area Description...................................................34<br>4.4.2.1 HccaInterruptTable............................................................................................34<br>4.4.2.2 HccaFrameNumber............................................................................................35<br>4.4.2.3 HccaDoneHead..................................................................................................35<br>4.5 Endpoint List Processing.................................................................................36<br>4.6 Transfer Descriptor Queue Processing...........................................................37<br>5. HOST CONTROLLER DRIVER................................................................................38<br>5.1 Host Controller Management............................................................................38<br>5.1.1 Initialization..............................................................................................................38<br>5.1.1.1 Load and Locate................................................................................................39<br>5.1.1.2 Verify Host Controller and Allocate Resources...................................................39<br>5.1.1.3 Take Control of Host Controller.........................................................................40<br>5.1.1.3.1 SMM Driver, Power-Up..............................................................................40<br>5.1.1.3.2 BIOS Driver................................................................................................40<br>5.1.1.3.3 OS Driver, SMM Active..............................................................................41<br>5.1.1.3.4 OS Driver, BIOS Active..............................................................................41<br>5.1.1.3.5 OS Driver, neither SMM nor BIOS.............................................................41<br>5.1.1.3.6 SMM Driver, Re-Entry................................................................................42<br>vii<br><br>OpenHCI - Open Host Controller Interface Specification for USB<br>5.1.1.4 Setup Host Controller........................................................................................42<br>5.1.1.5 Begin Sending SOFs...........................................................................................42<br>5.1.2 Operational States.....................................................................................................43<br>5.1.2.1 USBRESET..........................................................................................................43<br>5.1.2.2 USBOPERATIONAL..............................................................................................43<br>5.1.2.3 USBSUSPEND......................................................................................................43<br>5.1.2.4 USBRESUME.......................................................................................................44<br>5.2 Schedule.............................................................................................................44<br>5.2.1 Sample Host Controller Driver Definitions................................................................46<br>5.2.2 Miscellaneous Definitions..........................................................................................46<br>5.2.3 Host Controller Descriptors Definitions.....................................................................47<br>5.2.4 Host Controller Driver Descriptor Definitions...........................................................48<br>5.2.5 Host Controller Endpoints........................................................................................50<br>5.2.6 Host Controller Driver Internal Definitions................................................................51<br>5.2.7 Endpoint Descriptor Lists.........................................................................................54<br>5.2.7.1 Bulk and Control................................................................................................54<br>5.2.7.1.1 Adding........................................................................................................54<br>5.2.7.1.2 Removing....................................................................................................56<br>5.2.7.1.3 Pause...........................................................................................................59<br>5.2.7.2 Interrupt.............................................................................................................61<br>5.2.7.2.1 Polling Rate.................................................................................................64<br>5.2.7.2.2 Adding........................................................................................................66<br>5.2.7.2.3 Removing....................................................................................................66<br>5.2.7.2.4 Pause...........................................................................................................67<br>5.2.7.3 Isochronous.......................................................................................................67<br>5.2.7.3.1 Adding........................................................................................................68<br>5.2.7.3.2 Removing....................................................................................................68<br>5.2.7.3.3 Pause...........................................................................................................68<br>5.2.8 Transfer Descriptor Queues......................................................................................68<br>5.2.8.1 The NULL or Empty Queue...............................................................................68<br>5.2.8.2 Adding to a Queue.............................................................................................69<br>5.2.8.3 Removing from a Queue.....................................................................................73<br>5.2.8.4 Cancel................................................................................................................74<br>5.2.9 Done Queue..............................................................................................................75<br>5.2.10 USB Bandwidth Allocation.....................................................................................78<br>5.2.10.1 Scheduling Overrun Errors...............................................................................78<br>5.2.11 ControlBulkServiceRatio........................................................................................79<br>5.3 Host Controller Interrupt...................................................................................80<br>5.4 FrameInterval Counter.......................................................................................85<br>5.5 Root Hub............................................................................................................86<br>viii<br><br>OpenHCI - Open Host Controller Interface Specification for USB<br>6. HOST CONTROLLER..............................................................................................87<br>6.1 Introduction........................................................................................................87<br>6.2 USB States.........................................................................................................87<br>6.2.1 UsbOperational.........................................................................................................88<br>6.2.2 UsbReset..................................................................................................................89<br>6.2.3 UsbSuspend..............................................................................................................89<br>6.2.4 UsbResume...............................................................................................................89<br>6.3 Frame Management...........................................................................................90<br>6.3.1 Frame Timing............................................................................................................90<br>6.3.2 StartOfFrame (SOF) Token Generation.....................................................................91<br>6.3.3 HccaFrameNumber Update.......................................................................................91<br>6.4 List Processing..................................................................................................92<br>6.4.1 Priority.....................................................................................................................92<br>6.4.1.1 List Priority........................................................................................................93<br>6.4.1.1.1 Periodic Lists...............................................................................................93<br>6.4.1.1.2 Nonperiodic Lists........................................................................................93<br>6.4.1.2 Endpoint Descriptor Priority..............................................................................94<br>6.4.1.3 Transfer Descriptor Priority................................................................................95<br>6.4.2 List Service Flow......................................................................................................95<br>6.4.2.1 List Enabled Check............................................................................................95<br>6.4.2.2 Locating Endpoint Descriptors...........................................................................97<br>6.4.3 Endpoint Descriptor Processing................................................................................98<br>6.4.4 Transfer Descriptor Processing.................................................................................99<br>6.4.4.1 Isochronous Relative Frame Number Calculation................................................99<br>6.4.4.2 Packet Address and Size Calculation..................................................................99<br>6.4.4.3 Packet Transfer Time Check.............................................................................101<br>6.4.4.4 Largest Data Packet Counter Operation...........................................................102<br>6.4.4.5 Status Writeback..............................................................................................102<br>6.4.4.5.1 General Transfer Descriptor Status Writeback...........................................102<br>6.4.4.5.2 Isochronous Transfer Descriptor Status Writeback....................................103<br>6.4.4.6 Transfer Descriptor Retirement........................................................................103<br>6.4.5 Done Queue............................................................................................................104<br>6.4.5.1 Done Queue Interrupt Counter.........................................................................104<br>6.5 Interrupt Processing........................................................................................105<br>6.5.1 SchedulingOverrun Event........................................................................................105<br>6.5.2 WritebackDoneHead Event.....................................................................................106<br>6.5.3 StartOfFrame Event................................................................................................106<br>6.5.4 ResumeDetected Event...........................................................................................106<br>6.5.5 UnrecoverableError Event......................................................................................106<br>6.5.6 FrameNumberOverflow Event.................................................................................106<br>6.5.7 RootHubStatusChange Event..................................................................................107<br>6.5.8 OwnershipChange Event.........................................................................................107<br>ix<br><br>OpenHCI - Open Host Controller Interface Specification for USB<br>6.6 Root Hub..........................................................................................................107<br>7. OPERATIONAL REGISTERS.................................................................................108<br>7.1 The Control and Status Partition....................................................................109<br>7.1.1 HcRevision Register................................................................................................109<br>7.1.2 HcControl Register.................................................................................................109<br>7.1.3 HcCommandStatus Register....................................................................................112<br>7.1.4 HcInterruptStatus Register......................................................................................113<br>7.1.5 HcInterruptEnable Register....................................................................................115<br>7.1.6 HcInterruptDisable Register...................................................................................116<br>7.2 Memory Pointer Partition................................................................................117<br>7.2.1 HcHCCA Register...................................................................................................117<br>7.2.2 HcPeriodCurrentED Register.................................................................................117<br>7.2.3 HcControlHeadED Register...................................................................................118<br>7.2.4 HcControlCurrentED Register................................................................................118<br>7.2.5 HcBulkHeadED Register........................................................................................119<br>7.2.6 HcBulkCurrentED Register.....................................................................................119<br>7.2.7 HcDoneHead Register............................................................................................120<br>7.3 Frame Counter Partition..................................................................................120<br>7.3.1 HcFmInterval Register............................................................................................120<br>7.3.2 HcFmRemaining Register.......................................................................................121<br>7.3.3 HcFmNumber Register...........................................................................................122<br>7.3.4 HcPeriodicStart Register........................................................................................122<br>7.3.5 HcLSThreshold Register.........................................................................................123<br>7.4 Root Hub Partition...........................................................................................123<br>7.4.1 HcRhDescriptorA Register......................................................................................124<br>7.4.2 HcRhDescriptorB Register......................................................................................125<br>7.4.3 HcRhStatus Register...............................................................................................126<br>7.4.4 HcRhPortStatus[1:NDP] Register...........................................................................128<br>APPENDIX A—PCI INTERFACE................................................................................132<br>PCI CONFIGURATION...............................................................................................132<br>PCI Configuration Spaces for OpenHCI-compliant USB Host Controller.........133<br>COMMAND Register.......................................................................................................134<br>CLASS_CODE Register...................................................................................................134<br>BAR_OHCI Register........................................................................................................135<br>x<br><br>OpenHCI - Open Host Controller Interface Specification for USB<br>APPENDIX B—LEGACY SUPPORT INTERFACE SPECIFICATION........................136<br>OVERVIEW.................................................................................................................136<br>OPERATIONAL THEORY..........................................................................................137<br>Keyboard/Mouse Input..........................................................................................137<br>Keyboard Output...................................................................................................138<br>Emulation Interrupts..............................................................................................138<br>Mixed Environment.........................................................................................................139<br>Gate A20 Sequence.........................................................................................................139<br>SYSTEM REQUIREMENTS........................................................................................140<br>Host Controller Mapping.......................................................................................140<br>SMI Signaling.........................................................................................................141<br>Intercept Port 60h and 64h Accesses..................................................................141<br>Interrupts................................................................................................................141<br>Run-time Memory ..................................................................................................141<br>PROGRAMMING INTERFACE...................................................................................142<br>Modifications to existing registers......................................................................142<br>HcRevision Register........................................................................................................142<br>Legacy Support Registers....................................................................................142<br>HceInput Register............................................................................................................143<br>HceOutput Register.........................................................................................................143<br>HceStatus Register...........................................................................................................144<br>HceControl Register........................................................................................................145<br>IMPLEMENTATION NOTES.......................................................................................146<br>Emulation Interrupt Decode..................................................................................146<br>A20 Gate.................................................................................................................146
Intel USB 3.0/3.1可扩展主机控制器驱动程序是由英特尔开发的一种驱动程序,用于支持和管理计算机上的USB 3.0和USB 3.1接口。 USB 3.0和USB 3.1是用于连接外部设备的通用串行总线接口,具有更高的传输速度和更大的带宽。然而,这些接口在计算机上无法直接使用,需要相应的驱动程序来正确地识别和操作外部设备。 英特尔的USB 3.0/3.1可扩展主机控制器驱动程序为计算机提供了必要的软件支持,使USB 3.0和USB 3.1接口能够正常工作。它可以与系统硬件组件配合工作,确保外部设备在连接到计算机时能够正确地与系统进行通信。 该驱动程序具有许多功能和优势。首先,它能够提供高速的数据传输和更稳定的连接,使外部设备能够更快速地传输数据。其次,它支持热插拔功能,允许用户在计算机运行时连接和断开外部设备,而不需要重新启动计算机。 此外,该驱动程序还提供了一些安全性和稳定性功能,以确保计算机能够安全地与外部设备通信,并避免数据丢失或故障。它还可以提供更好的兼容性,使用户能够在计算机上连接各种不同类型的外部设备。 总而言之,英特尔USB 3.0/3.1可扩展主机控制器驱动程序是一种重要的软件组件,使计算机能够支持和管理USB 3.0和USB 3.1接口。它提供了更快速、更稳定和更安全的数据传输功能,使用户能够方便地连接和使用外部设备。

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