VerilogHDL.ADC0804有限状态机控制

`timescale 1us / 1ps
//
// Company:
// Engineer:
//
// Create Date: 08:07:51 03/26/2019
// Design Name:
// Module Name: ADC0809
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module ADC0809( clk, //20ns
rst_n,
EOC, //100usEOC
START, //100ns
OE, //
ALE, //
ADDR, //ADDB,ADDCADDA
DATA, //
clki,
DATA_R
);
output START,OE,ALE,clki;
input EOC,clk,rst_n;
input [7:0] DATA;
output [2:0] ADDR;
output [63:0] DATA_R;

reg START,OE,ALE,clki;
reg[2:0] ADDR;
reg[63:0] DATA_R;
reg[2:0] CS,NS;
reg[5:0] counter;
reg[3:0] cnt_EOCF;
reg[6:0] cnt_MXEOC;
localparam DEYTIM_EOCF=4’b1000; //20us
localparam DEYTIM_MAXEOC=7’b100_0000; //150us
/*********************************************************/
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
counter <= 0;
clki <= 0;
end

else if (counter ==12'd49) 
begin
   counter <= 0;
	clki <=~clki;

end

 else begin		
counter <= counter+1'b1;	
end

end

/*********************************************************************/
parameter IDLE=5’b000,
ALE_H=5’b001,
START_H=5’b010,
START_L=5’b011,
CHECK_END=5’b100,
GET_DATA=5’b101,
DATA_COM=5’b110;
/AD/

always@(posedge clki or negedge rst_n)
begin
if(!rst_n)
begin
cnt_EOCF<=4’b0000;
cnt_MXEOC<=7’b0000000;
end
else
case(CS)
START_L:
begin
if(cnt_EOCF4’b1001) cnt_EOCF<=4’b0000;
else cnt_EOCF<=cnt_EOCF+1’b1;
end
CHECK_END:
begin
if(cnt_MXEOC7’b100_0001) cnt_MXEOC<=7’b000_0000;
else cnt_MXEOC<=cnt_MXEOC+1’b1;
end
default:
begin
cnt_EOCF<=4’b0000;
cnt_MXEOC<=7’b0000000;
end
endcase
end

always @(posedge clki)
case(CS)
IDLE:
NS=ALE_H;
ALE_H:
NS=START_H;
START_H:
NS=START_L;
START_L:
if(cnt_EOCFDEYTIM_EOCF)
NS=CHECK_END;
else
NS=START_L;
CHECK_END:
if(EOC)
NS=GET_DATA;
else if(cnt_MXEOCDEYTIM_MAXEOC)
NS=GET_DATA; //cnt_MXEOC<=0;
else
NS=CHECK_END;
GET_DATA:
NS=DATA_COM;
DATA_COM:
NS=IDLE;
default:
NS=IDLE;
endcase

always @(posedge clki or negedge rst_n)
if(!rst_n)
CS<=IDLE;
else
CS<=NS;

always @(posedge clki or negedge rst_n)
if(!rst_n)
begin
OE<=0;
START<=0;
ALE<=0;
ADDR<=3’b000;
DATA_R<=64’b0;
end
else
case(NS)
IDLE: //
begin
OE<=0;
START<=0;
ALE<=0;
end
ALE_H:
begin
OE<=0;
START<=0;
ALE<=1;
end
START_H:
begin
OE<=0;
START<=1; //
ALE<=1;
end
START_L:
begin
OE<=0;
START<=0;
ALE<=0;//,ALE
end
CHECK_END:
begin
OE<=0;
START<=0;
ALE<=0;
end
GET_DATA:
begin
OE<=1; //
case(ADDR)
3’b000: DATA_R[7:0]<=DATA;
3’b001: DATA_R[15:8]<=DATA;
3’b010: DATA_R[23:16]<=DATA;
3’b011: DATA_R[31:24]<=DATA;
3’b100: DATA_R[39:32]<=DATA;
3’b101: DATA_R[47:40]<=DATA;
3’b110: DATA_R[55:48]<=DATA;
3’b111: DATA_R[63:56]<=DATA;
endcase
START<=0;
ALE<=0;
end
DATA_COM:
begin
OE<=0; //
//DATA_R<=(DATA_R<<8);
ADDR<=ADDR+1’b1;
START<=0;
ALE<=0;

	end
default:
  begin
      OE<=0;
      START<=0;
      ALE<=0;
	   ADDR<=3'b000;
		DATA_R<=64'b0;
  end
endcase  

endmodule