qq_40166917的博客

原创 Verilog语言实现4位移位乘法器

modulemulti_4(mplr,mcnd,clk,reset,done,acc,count,mul_state,next_state);      output  done;      output [7:0] acc;      output   [2:0] count;      output [1:0] mul_state,next_state;      input [3:0] mp...