Chapter 1 Overview

1.What is Design-for-Test?

• 可测试性（Testability） 是一种设计属性，用来衡量创建一个程序以全面测试制造出的芯片质量的难易程度。 传统上，设计和测试过程是分开的，只有在设计周期的最后阶段才考虑测试。但是在当代的设计流程中，测试与设计在IC流程的早期合并，创建了称为DFT（Design-for-test 的流程。

• 可测试性电路包括可控制性和可观察性（ controllable and observable）。在可测试的设计中，在原始输入端（primary inputs）设置特定的值，使得原始输出端（primary outputs）上的值能够表明内部电路是否正常工作。

• 为了确保电路设计具有最大程度的可测试性，设计人员必须在开发过程的特定阶段采用特定的DFT技术。

2.DFT Strategies

At the highest level, there are two main approaches to DFT: ad hoc and structured. The
following subsections discuss these DFT strategies

2.1 Ad Hoc DFT

Ad hoc DFT implies using good design practices to enhance the testability of a design without making major changes to the design style.Some ad hoc techniques include:

• Minimizing redundant logic
• Minimizing asynchronous logic
• Isolating clocks from the logic
• Adding internal control and observation points
  Using these practices throughout the design process improves the overall testability of your design. However, using structured DFT techniques with the Mentor Graphics DFT tools yields far greater improvement. Thus, the remainder of this document concentrates on structured DFT techniques.
  
  

2.2 Structured DFT

• Structured DFT provides a more systematic and automatic approach to enhancing design
  testability.
• Structured DFT’s goal is to increase the controllability and observability of a circuit. Various methods exist for accomplishing this.
  • The most common is the scan design technique, which modifies the internal sequential circuitry of the design.
  • You can also use the Built-in Self-Test (BIST) method, which inserts a device’s testing function within the device itself.
  • Another method is boundary scan, which increases board testability by adding circuitry to a chip. “Scan and ATPG Basics” describes these methods in detail.
    

3.Top-Down Design Flow with DFT

As Figure 1-1 shows, the first task in any design flow is creating the initial RTL-level design, through whatever means you choose. In the Mentor Graphics environment, you may choose to create a high-level Verilog description using ModelSim® or a schematic using Design Architect®. You then verify the design’s functionality by performing a functional simulation, using ModelSim or another vendor’s Verilog simulator.

At this point in the flow you are ready to insert internal scan circuitry into your design using Tessent Scan®. You may then want to re-verify the timing because you added scan circuitry. Once you are sure the design is functioning as desired, you can generate test patterns. You can use the ATPG tool to generate a test pattern set in the appropriate format.
Now you should verify that the design and patterns still function correctly with the proper
timing information applied. You can use ModelSim or some other simulator to achieve this
goal. You may then have to perform a few additional steps required by your ASIC vendor
before handing the design off for manufacture and testing.