makefile

Reference from：史上最强最细腻的linux嵌入式C语言学习教程【李慧芹老师】_哔哩哔哩_bilibili   p70

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And: Sorry about my Chinglish cuz there has not a chinese input language in ubuntu os...XD

****
original version 1: 
****
mytool:main.o tool1.o tool2.o
    gcc main.o tool1.o tool2.o -o mytool

main.o:main.c
    gcc main.c -c -Wall -g -o main.o 
too1.o:tool1.c
    gcc tool1.c -c -Wall -g -o tool1.c
too2.o:tool2.c
    gcc tool2.c -c -Wall -g -o tool2.c

clean:
    rm *.o mytool  -rf
    
-Wall -g : warning all and debug
-----------------------------------------------------
// define phase 

//use A=a to define one or several project names\chars
OBJS=main.o tool1.o tool2.o
CC=gcc 
// CC default = gcc , you can not to type "CC = gcc"

//Complie phase 

mytool:$(OBJS)
    $(CC) $(OBJS) -o mytool
// use $(A) to replace the original chars 通配符
// $(CC) translate to gcc
// $(OBJS) translate to main.o tool1.o tool2.o

main.o:main.c
    $(CC) main.c -c -Wall -g -o main.o 
too1.o:tool1.c
    $(CC) tool1.c -c -Wall -g -o tool1.c
too2.o:tool2.c
    $(CC) tool2.c -c -Wall -g -o tool2.c

clean:
    //rm *.o mytool  -rf
    $(RM) *.o mytool -r
//make tool defined RM = rm -f , so we use $(RM) to replace rm -f 

****
so version2:
****

OBJS=main.o tool1.o tool2.o
CC=gcc 

mytool:$(OBJS)
    $(CC) $(OBJS) -o mytool

main.o:main.c
    $(CC) main.c -c -Wall -g -o main.o 
too1.o:tool1.c
    $(CC) tool1.c -c -Wall -g -o tool1.c
too2.o:tool2.c
    $(CC) tool2.c -c -Wall -g -o tool2.c

clean:    
    $(RM) *.o mytool -r
-----------------------------------------------------
// we can easily see that there are idential -c -Wall -g in the several lines
// so we can also type an equaltaiton to define the chars
// in the define phase we usrally use CFLAGS to replace the appendence 
// CFLAGS +=-c -Wall -g 

OBJS=main.o tool1.o tool2.o
CC=gcc 
CFLAGS +=-c -Wall -g 

mytool:$(OBJS)
    $(CC) $(OBJS) -o mytool 
// Addition $(OBJS) appeared on previous line, usually we use "^" to instead the previous-line-appeared chars, and obviously this replacement is absolutely obviously.(XD)
// so them turning to :

mytool:$(OBJS)
    $(CC) $^ -o mytool 
// and the target filename, in this exam is the "mytool" and it's also a relative name and usually the name is same as the original name not include the suffix. we use "@" to relace.Do Not forget the "$".:)
// so them turning to :

mytool:$(OBJS)
    $(CC) $^ -o $@ 

main.o:main.c
    $(CC) $^ $(CFLAGS) -o $@
too1.o:tool1.c
    $(CC) $^ $(CFLAGS) -o $@
too2.o:tool2.c
    $(CC) $^ $(CFLAGS) -o $@

clean:    
    $(RM) *.o mytool -r

****
so version3:
****

OBJS=main.o tool1.o tool2.o
CC=gcc 
CFLAGS +=-c -Wall -g 

mytool:$(OBJS)
    $(CC) $^ -o $@ 

main.o:main.c
    $(CC) $^ $(CFLAGS) -o $@
too1.o:tool1.c
    $(CC) $^ $(CFLAGS) -o $@
too2.o:tool2.c
    $(CC) $^ $(CFLAGS) -o $@

clean:    
    $(RM) *.o mytool -r
-----------------------------------------------------
// AND!
// From now on! we got a same line several times!
// "$(CC) $^ $(CFLAGS) -o $@" this line 
// AND!
// We found a regulation of the phase two.
// We compile base on the same rule: 
//    XX.o:XX.c
//          $(CC) $^ $(CFLAGS) -o $@
// CC=gcc 
//The char "%" will replace to the (OBJS)'s arrtribution respectively.

****
version 4:
****

OBJS=main.o tool1.o tool2.o
CFLAGS +=-c -Wall -g 

mytool:$(OBJS)
    $(CC) $^ -o $@ 

%.o:%.c   
    $(CC) $^ $(CFLAGS) -o $@

clean:    
    $(RM) *.o mytool -r
-----------------------------------------------------