Accellera’s recently released UVM may change the future of verification, as verification methodology seems to be consolidated in this UVM. This post will provide a simple tutorial on this new verification methodology. Rather than focusing on AXI, OCP, or other system buses in existence, this tutorial will be based on the hypothetical example of a jelly-bean generator. The test bench will generate many jelly-bean flavors in a constrained random manner and the system will evaluate palatable flavors. This does not require the knowledge of any system bus.
The verification components used in the process will be described below.
Verification Components
The left figure shows the relationship of the verification components. The jelly_bean_taster
is the design-under-test (DUT) module.
The jelly_bean_sequencer
will create jelly-bean recipes and send them to the jelly_bean_driver
. From the information provided in the recipe, the driver creates jelly beans. The driver passes the jelly beans through the jelly-bean interface (jelly_bean_if
) to the jelly_bean_taster
, which will check the jelly-bean taste.
Concurrently, as the jelly beans are being created, the jelly_bean_monitor
will capture the flavor and color of the recently produced. This information will be passed down to the jelly-bean functional coverage subscriber, referred to as the jelly_bean_fc_subscriber
. The subscriber records and totals the jelly beans based on their color and flavor.
The jelly_bean_scoreboard
is a component that checks if the jelly_bean_taster
is responding correctly. The scoreboard subscribes the information from the jelly_bean_monitor
.
Class Diagram of Verification Components
The second figure shows the verification components in a class diagram. The light blue boxes refer to the classes in the UVM basic class library, while the darker boxes indicate the classes created in this tutorial.
Though the post ends here, the next will show the structure of the jelly-bean recipes.