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RSS订阅翻译 UVM Tutorial for Candy Lovers – 12. Analysis Port
This post will explain how analysis port and analysis export work.InAgent, we connected the analysis port (jb_ap) of the jelly-bean monitor (jb_mon) to the analysis port (jb_ap) of the jelly-bean a...
2019-12-15 15:55:50
292
翻译 UVM Tutorial for Candy Lovers – 11. Sequence Item Port
A UVM driver and a UVM sequencer are connected using a UVM sequence item port and an export. This post will explain how the sequence item port works.InAgent, we connected the sequence item port (seq...
2019-12-15 15:51:37
354
翻译 UVM Tutorial for Candy Lovers – 10. Inside Candy Factory
UVM factory is used to create UVM objects and components. This post will explain the UVM factory using jelly beans (as you expected) and reveal what happens behind the scenes in the factory.::type_i...
2019-12-01 10:43:50
340
翻译 UVM Tutorial for Candy Lovers – 9. Register Abstraction
This post will explain how to use the UVM Register Abstraction Layer (RAL) to generate register transactions.The figure below shows the verification platform used for this post. Among other things, t...
2019-12-01 10:38:55
417
翻译 UVM Tutorial for Candy Lovers – 8. Configurations
This post will give an explanation on UVM configuration objects, since the earlier posts did not cover much on them.The jelly-bean verification platform uses two kinds of configuration objects,jelly...
2019-12-01 10:25:03
228
翻译 UVM Tutorial for Candy Lovers – 7. Virtual Sequence
Did you know the mix of two lemon and two coconut jelly beans will create the flavor of lemon meringue pie? And the mix of two strawberry and two vanilla jelly beans will create the flavor of strawber...
2019-12-01 10:12:15
324
SVA_ The Power of Assertions in SystemVerilog
2018-12-26
SystemVerilog Assertions and Functional Coverage_ Guide to Language
2018-12-26
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