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RSS订阅原创 如何dump task中的波形
interface tod_if(input bit ts_clk);..//tranmitbit [79:0] ts_cnt=0;logic [79:0] ts_cnt_lock;logic start_flag;logic trigger_flag;logic start_finish;logic tran_finish;logic [1:0] start_cnt;logic [7:0] tran_cnt;logic
2020-06-29 16:01:11
1649
原创 简单回归shell脚本
简单回归shell脚本```powershellseed=$1run_opt="-reportstats"echo "seed=$seed"while read LINEdo#echo $LINEfirstbyte=${LINE:0:1}#echo $firstbyteif [ $firstbyte == "#" ]; then echo "not valid case"else #echo "valid case" echo $LINE ./simv +
2020-05-28 11:57:21
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apb_svt_uvm_getting_started.pdf
This Getting Started Guide presents information about integrating the VC VIP for APB (referred to as VIP)
into testbenches that are compliant with the SystemVerilog Universal Verification Methodology (UVM). You
are assumed to be familiar with the AMBA APB protocol and UVM.
2020-09-15
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