#问题及解决方案整理# | FPGA | 朋友亲测-帮发 | 解决 modelsim is existing with code 7 问题

当使用Modelsim仿真时遇到modelsimisexistingwithcode7错误,可能是因为电脑用户名包含中文。解决方法包括创建新的管理员账户,重命名用户文件夹,修改注册表中ProfileImagePath的值,然后重启电脑。此问题通常影响软件安装和运行,如Ansys,需要以管理员权限运行。
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项目场景:

运行环境:modelsim

问题描述:

朋友用modelsim仿真遇到 modelsim is existing with code 7 问题。

帮助遇到同样问题的朋友。

错误提示:

modelsim is existing with code 7

现象:

出现错误。

原因分析:

可能是电脑用户名中英文不对。

解决方案:

参考在win10家庭版中修改C盘用户文件夹中文名为英文名
win10家庭版修改方法如下:

  1. 假设需要改名的用户账户为A账户,更改用户文件夹名称之前必须先添加一个用户账户(可以新建一个微软账户,假设为B账户),并将B账户由标准账户升级为管理员账户;
  2. 注销A账户退出,重启电脑用B账户登录; 打开我的电脑-C盘-用户-A用户文件夹,这时候可以重命名了,如果不行,再重启一下。
  3. 用Windows键+r键打开“运行”,输入regedit,点确定。
  4. 找到注册表中的这个目录:HKEY_LOCAL_MACHINE\SOFTWARE\Microsoft\WindowsNT\CurrentVersion\ProfileList(仔细看清楚),在ProfileList下的几个子目录中找到那个里面写着你旧用户文件夹的子目录,双击ProfileImagePath,将A账户中文名改为英文名。
  5. 最后,重启电脑用A账户登录,即可大功告成。
  6. 用上面的方法安装完成Ansys后,需要以管理员身份运行Ansys。
Mentor, a Siemens business, has unveiled ModelSim 10.7, is unified debug and simulation environment gives today's FPGA designers advanced capabilities in a productive work environment. About Mentor Graphics ModelSim. Modelsim HDL simulator provides FPGA customers with and easy cost-effective way to speed up FPGA development, lab bring up and test. Many FPGA designers go to the lab before adequately vetting their design. This means weeks or even months of inefficient debugging time in the lab. Testing in the lab has limited visibility of the signals in design. It can take 8 hours to do a place and route just instrument additional signals or make a small bug fix. With simulation the debug loop is much faster and there is complete visibility into the signals in the design. Simulation enables a much higher quality FPGA design before entering the lab allowing time spent during lab debug much more productive and focused. In addition to supporting standard HDLs, ModelSim increases design quality and debug productivity. ModelSim’s award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code. The graphical user interface is powerful, consistent, and intuitive. All windows update automatically following activity in any other window. For example, selecting a design region in the Structure window automatically updates the Source, Signals, Process, and Variables windows. You can edit, recompile, and re-simulate without leaving the ModelSim environment. All user interface operations can be scripted and simulations can run in batch or interactive modes. ModelSim simulates behavioral, RTL, and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing provided by the Standard Delay Format (SDF).
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