松翰单片机的使用

工程说明

芯片型号选择

CHIP	SN8P2711A ;(SOP_14)

编译选项

在这里插入图片描述

//{{SONIX_CODE_OPTION
	.Code_Option	LVD		        LVD_H		; 2.4V Reset Enable LVD36 bit of PFLAG for 3.6V Low Voltage Indicator
	.Code_Option	Reset_Pin	    P04         ; Reset :使能外部复位引脚功能。当下降沿触发时,系统复位;P04 :使能 P0.4 为单向输入引脚。此时禁止外部复位引脚功能。
	.Code_Option	Watch_Dog	    Enable		; Normal mode: Enable Watchdog Green and Sleep mode: Stop Watchdog
	.Code_Option	High_Clk	    IHRC_16M	; Internal 16M RC Oscillator
	.Code_Option	Fcpu		    #7          ; Fcpu = Fosc/16
	.Code_Option	Security	    Enable
	.Code_Option	Noise_Filter	Enable
//}}SONIX_CODE_OPTION

复位后系统初始化

.CODE                                                   ; 代码部分
                    ORG            000H                 ; CODE SECTION START(代码部分起始位置)
                    JMP            RESET                ; 跳转到 RESET 位置运行
                    ORG            008H                 ; 如果代码运行过程产生中断才会跳转到此处执行
                    JMP            INT_SERVICE          ; Exit the interrupt routine
                    ORG            010H
;========================================================================================================
RESET:
	            MOV		    A, #0x5A
	            B0MOV	    WDTR, A		; Clear watchdog timer(在编译选型中已经启动了看门狗,所以此处只需要喂狗即可以了)
                CALL        DLY_50MS    ; 延时(一般是等待系统稳定)
	            MOV 	    A,#07h		; 
   	            B0MOV 	    STKP,A		; Initial stack pointer and disable global interrupt
	            CLR		    PFLAG		; pflag = x,x,x,x,x,c,dc,z
	            MOV     	A,#00h		; Initial system mode
	            B0MOV       OSCM,A

堆栈指针 STKP 是一个 3 位寄存器,存放被访问的堆栈单元地址。
在这里插入图片描述
Bit[2:0] STKPBn :堆栈指针(n = 0 ~ 2)。
Bit 7 GIE :全局中断控制位。
0 = 禁止;
1 = 使能。

程序状态寄存器PFLAG,在这里主要是给C、DC、Z位置零
在这里插入图片描述
Bit 2 C:进位标志。
1 = 加法运算后有进位、减法运算没有借位发生或移位后移出逻辑“1”或比较运算的结果 ≥ 0;
0 = 加法运算后没有进位、减法运算有借位发生或移位后移出逻辑“0”或比较运算的结果 < 0。
Bit 1 DC:辅助进位标志。
1 = 加法运算时低四位有进位,或减法运算后没有向高四位借位;
0 = 加法运算时低四位没有进位,或减法运算后有向高四位借位。
Bit 0 Z:零标志。
1 = 算术/逻辑/分支运算的结果为零;
0 = 算术/逻辑/分支运算的结果非零。
OSCM寄存器 寄存器 OSCM 控制振荡器的状态和系统的工作模式。
在这里插入图片描述
Bit 1 STPHX :高速振荡器控制位。
0 = 运行;
1 = 停止,内部低速 RC 振荡器仍然运行。
Bit 2 CLKMD :系统时钟模式控制位。
0 = 普通(双时钟)模式,高速时钟作为系统时钟;
1 = 低速模式,低速时钟作为系统时钟。
Bit[4:3] CPUM[1:0] :CPU 工作模式控制位。
00 = 普通模式;
01 = 睡眠模式;
10 = 绿色模式;
11 = 系统保留。

RAM初始化

JMP_INIT_RAM:
                    CLR             Y
                    B0MOV           Z,#0x3F             ; CLR 3F~00H
JMP_INIT_RAM_LOOP:
                    CLR             @YZ                 ; 给@YZ地址清零,第一次地址为 0x3F
                    DECMS           Z                   ; Z ← Z - 1,如果 Z = 0,则跳过下一条指令。  
                    JMP             JMP_INIT_RAM_LOOP   ; 若 Z 不为 0,则循环
                    CLR             @YZ                 ; 清地址为 0x00 处内容

                    RET                                 ; 退出函数

@YZ:RAM 数据寻址指针
在这里插入图片描述

IO口初始化

                    MOV             A,#0x0C             ; P0.2,P0.3 output,Others all input
                    B0MOV           P0M,A               ; 
                    MOV             A,#0xF3             ; P0.2=1,P0.3=1
                    B0MOV           P0UR,A
                    MOV             A,#0x00
                    MOV             P0,A                ; P0.2=0,P0.3=0

在这里插入图片描述
寄存器 PnM 控制 I/O 口的工作模式。
Bit[7:0] PnM[7:0] :Pn 模式控制位(n = 0~5)。
0 = 输入模式;
1 = 输出模式。
在这里插入图片描述
I/O 引脚内置上拉电阻,仅在输入模式下有效。I/O 引脚的上拉电阻由 PnUR 寄存器控制,
PnUR 寄存器为
0 时,禁止上拉电阻;
1 时,使能上拉电阻。

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1.1 FEATURES  Memory configuration  Four 8-bit timer. (T0, TC0, TC1, TC2). Flash ROM size: 6K x 16 bits. Including EEROM T0: Basic timer. emulation. (In system programming) TC0: Timer/counter/PWM0. RAM size: 512 x 8 bits. TC1: Timer/counter/PWM1.  8 levels stack buffer. TC2: Timer/counter/PWM2  13 interrupt sources  3 channel duty/cycle programmable PWM to 11 internal interrupts: T0, TC0, TC1, TC2, T1, ADC, Generate PWM, Buzzer and IR carrier signals. SIO, MSP, UTX(UART TX), URX(UART RX), WAKE (PWM0~2). 2 external interrupts: INT0, INT1  One 16-bit timer (T1) with capture timer function.  Multi-interrupt vector structure.  12- channel 10-bit SAR ADC. Each of interrupt sources has a unique interrupt vector.  Serial Interface: SIO, UART, MSP  Build in Embedded ICE function.  I/O pin configuration Bi-directional: P0, P1, P4, P5.  Four system clocks Wakeup: P0, P1 level change. External high clock: RC type up to 10MHz Pull-up resisters: P0, P1, P4, P5. External high clock: Crystal type up to 16MHz External interrupt: P0.0, P0.1 Internal high clock: RC type 16MHz ADC input pin: AIN0~AIN11. Internal low clock: RC type 16KHz  Four operating modes  Fcpu (Instruction cycle) Normal mode: Both high and low clock active Fcpu = Fhosc/1, Fhosc/2, Fhosc/4, Fhosc/8, Fhosc/16, Slow mode: Low clock only Fhosc/32, Fhosc/64, Fhosc/128 Sleep mode: Both high and low clock stop  On chip watchdog timer and clock source Green mode: Periodical wakeup by timer  1.8V/2.4V/3.3V 3-level LVD with trim.  Package (Chip form support) PDIP 32 pin  Powerful instructions LQFP 32 pin Instruction’s length is one word. QFN 32 pin Most of instructions are one cycle only. SKDIP 28 pin All ROM area JMP instruction. SOP 28 pin All ROM area lookup table function (MOVC). SSOP 28 pin QFN 28 pin DIP 20 pin SOP 20 pin
1.1 FEATURES  Memory configuration  Four 8-bit timer. (T0, TC0, TC1, TC2). Flash ROM size: 6K x 16 bits. Including EEROM T0: Basic timer. emulation. (In system programming) TC0: Timer/counter/PWM0. RAM size: 512 x 8 bits. TC1: Timer/counter/PWM1.  8 levels stack buffer. TC2: Timer/counter/PWM2  13 interrupt sources  3 channel duty/cycle programmable PWM to 11 internal interrupts: T0, TC0, TC1, TC2, T1, ADC, Generate PWM, Buzzer and IR carrier signals. SIO, MSP, UTX(UART TX), URX(UART RX), WAKE (PWM0~2). 2 external interrupts: INT0, INT1  One 16-bit timer (T1) with capture timer function  Multi-interrupt vector structure.  12- channel 10-bit SAR ADC. Each of interrupt sources has a unique interrupt vector.  Serial Interface: SIO, UART, MSP  Build in Embedded ICE function.  I/O pin configuration Bi-directional: P0, P1, P4, P5.  Four system clocks Wakeup: P0, P1 level change. External high clock: RC type up to 10MHz Pull-up resisters: P0, P1, P4, P5. External high clock: Crystal type up to 16MHz External interrupt: P0.0, P0.1 Internal high clock: RC type 16MHz ADC input pin: AIN0~AIN11. Internal low clock: RC type 16KHz  Four operating modes  Fcpu (Instruction cycle) Normal mode: Both high and low clock active Fcpu = Fhosc/1, Fhosc/2, Fhosc/4, Fhosc/8, Fhosc/16, Slow mode: Low clock only Fhosc/32, Fhosc/64, Fhosc/128 Sleep mode: Both high and low clock stop  On chip watchdog timer and clock source Green mode: Periodical wakeup by timer  1.8V/2.4V/3.3V 3-level LVD with trim.  Package (Chip form support) PDIP 32 pin  Powerful instructions LQFP 32 pin Instruction’s length is one word. QFN 32 pin Most of instructions are one cycle only. SKDIP 28 pin All ROM area JMP instruction. SOP 28 pin All ROM area lookup table function (MOVC). SSOP 28 pin QFN 28 pin DIP 20 pin SOP 20 pin

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