Windows tcl运行Vitis Vision例程-CSDN博客

本文链接：https://blog.csdn.net/qq_42986755/article/details/127052949

软件环境

Vitis HLS 2021.2 Windows OpenCV环境配置
 Vitis Library下载链接

步骤

在D:\VitisLib\Vitis_Libraries\vision\L1\examples\dilation\目录下新建文件settings.tcl；

set XPART xcu250-figd2104-2L-e
set CSIM 1
set CSYNTH 1
set COSIM 0
set VIVADO_SYN 0
set VIVADO_IMPL 0
set QOR_CHECK 0
set OPENCV_INCLUDE "D:/VitisLib/opencv/install/include"
set OPENCV_LIB "D:/VitisLib/opencv/install/x64/mingw/lib"
set XF_PROJ_ROOT "D:/VitisLib/Vitis_Libraries/vision"

打开Vitis HLS Command Prompt运行

cd D:\VitisLib\Vitis_Libraries\vision\L1\examples\dilation
vitis_hls -f run_hls.tcl

遇到报错
修改run_hls.tcl，为opencv_imgcodecs等加上版本号440

#
# Copyright 2019 Xilinx, Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#

source settings.tcl

set PROJ "dilation.prj"
set SOLN "sol1"

if {![info exists CLKP]} {
  set CLKP 3.3
}

open_project -reset $PROJ

add_files "${XF_PROJ_ROOT}/L1/examples/dilation/xf_dilation_accel.cpp" -cflags "-I${XF_PROJ_ROOT}/L1/include -I ${XF_PROJ_ROOT}/L1/examples/dilation/build -I ./ -D__SDSVHLS__ -std=c++0x" -csimflags "-I${XF_PROJ_ROOT}/L1/include -I ${XF_PROJ_ROOT}/L1/examples/dilation/build -I ./ -D__SDSVHLS__ -std=c++0x"
add_files -tb "${XF_PROJ_ROOT}/L1/examples/dilation/xf_dilation_tb.cpp" -cflags "-I${OPENCV_INCLUDE} -I${XF_PROJ_ROOT}/L1/include -I ${XF_PROJ_ROOT}/L1/examples/dilation/build -I ./ -D__SDSVHLS__ -std=c++0x" -csimflags "-I${XF_PROJ_ROOT}/L1/include -I ${XF_PROJ_ROOT}/L1/examples/dilation/build -I ./ -D__SDSVHLS__ -std=c++0x"
set_top dilation_accel

open_solution -reset $SOLN

set_part $XPART
create_clock -period $CLKP

if {$CSIM == 1} {
  csim_design -ldflags "-L ${OPENCV_LIB} -lopencv_imgcodecs440 -lopencv_imgproc440 -lopencv_core440 -lopencv_highgui440 -lopencv_flann440 -lopencv_features2d440" -argv " ${XF_PROJ_ROOT}/data/128x128.png "
}

if {$CSYNTH == 1} {
  csynth_design
}

if {$COSIM == 1} {
  cosim_design -ldflags "-L ${OPENCV_LIB} -lopencv_imgcodecs440 -lopencv_imgproc440 -lopencv_core440 -lopencv_highgui440 -lopencv_flann440 -lopencv_features2d440" -argv " ${XF_PROJ_ROOT}/data/128x128.png "
}

if {$VIVADO_SYN == 1} {
  export_design -flow syn -rtl verilog
}

if {$VIVADO_IMPL == 1} {
  export_design -flow impl -rtl verilog
}

exit

重新运行

vitis_hls -f run_hls.tcl
vitis_hls -p dilatiom.prj

C仿真通过
前往D:\VitisLib\Vitis_Libraries\vision\L1\examples\dilation\dilation.prj\sol1\csim\build查看C仿真结果

参考

链接: Vitis HLS 2020.2使用Vitis Vision实例代码实现图像处理dilation