Cordic算法的FPGA实现（附代码）_cordic quartus csdn-CSDN博客

本文链接：https://blog.csdn.net/qq_43538094/article/details/97801318

本文主要介绍了Cordic算法在FPGA中的实现，包括控制模块和计算模块的设计，通过仿真得到了期望的结果。适合FPGA初学者参考。

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FPGA新手，请多多指教
原理啥的就懒得说了，我看的是这个网页，比较详细
https://www.cnblogs.com/ninghechuan/p/8681006.html?utm_source=tuicool&utm

控制模块

module control(
    input [6:0]target,
	 input rst,
	 input clk,
	 input signed [26:0] xi,
	 input signed [26:0] yi,
	 input triggle,
	 
	 output reg [3:0] cnt,
	 output reg [26:0] cos_result,
    output reg signed [26:0] sin_result,
	 output reg [26:0]target_angle,
	 output reg cnt_start
	 );

reg [2:0] state;

parameter idle=3'b001;
parameter calculation=3'b010;
parameter finish=3'b100;


		always@(posedge rst or posedge clk)
			if(rst) begin
				state<=idle;
				target_angle<=0;
				cnt_start<=0;
				cos_result<=0;
				sin_result<=0;
				end
			else begin
					case(state)
						idle:begin 
								if(triggle) begin
									state<=calculation;
									target_angle<=(target<<<20);
									cnt_start<=1;
									end
								else begin
										state<=idle;
										cnt_start<=0;
									end
								end
							
						calculation:begin 
									if(cnt==15) begin 
										state<=finish;
										cnt_start<=0;
										end
									else begin
										state<=calculation;
										cnt_start<=1;
										end
								end
								
						finish:begin 
								state<=idle;
								cos_result<=xi;
								sin_result<=yi;
								end
							default:state<=idle;
						endcase
					end
					
		always@(posedge rst or posedge clk)
			if(rst) begin cnt<=0;
			end 
			else if(cnt_start) cnt<=cnt+1;
			else if(cnt==15) cnt<=0