用D触发器设计可重叠101序列检测器,同时用verilog开发该模块,并开发测试程序
分析设计要求,列出全部可能状态:
- 未收到一个有效位(0):S0
- 收到一个有效位(1):S1
- 连续收到两个有效位(10):S2
- 连续收到三个有效位(101):S3
状态转移图:
未经作者同意,不得转载
实例代码:
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2019/10/27 10:24:45
// Design Name:
// Module Name: ozo
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module ozo(
input x, clk, rst,
output y
);
reg y;
reg [1:0] currentstate, nextstate;
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;
always@(posedge clk or negedge rst) //
begin
if(!rst)
currentstate <= S0;
else
currentstate <= nextstate;
end
always@(currentstate or x or rst) //
begin
if(!rst)
nextstate = S0;
else
begin
case(currentstate)
S0:nextstate = (x==1)?S1:S0;
S1:nextstate = (x==0)?S2:S0;
S2:nextstate = (x==1)?S3:S0;
S3:nextstate = (x==1)?S1:S0;
default:nextstate = S0;
endcase
end
end
always@(rst or currentstate) //
begin
if(!rst)
y = 0;
else
case(currentstate)
S0:y = 0;
S1:y = 0;
S2:y = 0;
S3:y = 1;
default:y = 0;
endcase
end
仿真代码
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2019/10/27 10:27:38
// Design Name:
// Module Name: ozo_t
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module ozo_t(
);
reg clk,rst;
reg x;
wire y;
ozo ch(.clk(clk),.rst(rst),.x(x),.y(y));
initial begin
clk = 0;
rst = 1;
#5 rst = 0;
#3 rst = 1;
#40 x = 1;
#40 x = 1;
#40 x = 0;
#40 x = 1;
#40 x = 1;
#40 x = 0;
#40 x = 0;
#40 x = 1;
#40 x = 0;
#40 x = 1;
#40 x = 0;
#40 x = 0;
#40 x = 1;
#40 x = 0;
#40 x = 0;
#40 x = 1;
#40 x = 0;
#40 x = 1;
#40 x = 0;
end
仿真结果
未经原作者同意,不得转载。