HDLBits练习记录1——Fsm ps2data

        题目链接：Fsm ps2data - HDLBits (01xz.net)

        这道题应该注意的是题目中给的波形图中每个状态对应的一个完整周期中输入in不变，而实际上testbench中的in每个半周期都不同。结合出错时给出的波形图发现输出应该是时序的，应将每个状态下的输入in[7:0]寄存，最终拼起来作为输出。

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //

    parameter s0 = 2'b00, s1 = 2'b01, s2 = 2'b10;
    reg [1:0] state,next_state;
    reg[7:0] byte1, byte2, byte3;
    // State transition logic (combinational)
    always@(*)begin
        case(state)
            s0:begin next_state = in[3]? s1 : s0;end
            s1:begin next_state = s2;end
            s2:begin next_state = s0;end
            default:next_state = s0;
        endcase
    end
	
    // State flip-flops (sequential)
    always@(posedge clk)begin
        if(reset)
            state <= s0;
        else
            state <= next_state;
    end
    // Output logic
    reg done2;
    always@(posedge clk)begin
        if(reset)
            done2 <= 0;
        else
            done2 <= (state == s2);
    end
            
    assign done = done2;

    always@(posedge clk )begin
        if(reset)begin
            byte1 <= 0;
        	byte2 <= 0;
        	byte3 <= 0;
        end
        else begin
        	case(next_state)
                s1:begin byte1 <= in;byte2 <= byte2;byte3 <= byte3;end
                s2:begin byte2 <= in;byte1 <= byte1;byte3 <= byte3;end
                s0:begin byte3 <= (state == s2)? in : 8'hxx; byte1 <= byte1; byte2 <= byte2;end
        	endcase
        end
    end
    
    assign out_bytes = done? {byte1,byte2,byte3}: 24'hxxxxxx;
        
            
        
    
endmodule

        有其他的想法欢迎交流。