2021-06-30

https://www.bilibili.com/video/BV1DL411p7sj/
本实验为自主实验作业
设计代码为
module Add_full_unit_delay(output c_out,sum,input a,b,c_in);
wire w1,w2,w3;
ADD_half_unit_delay M1(w2,w1,a,b);
ADD_half_unit_delay M2(w3,sum,w1,c_in);
or #1 M3(c_out,w2,w3);
endmodule
测试代码为

module ADD_half_unit_delay (output c_out,sum,input a,b);
xor #1 M1(sum,a,b);
and #1 M2(c_out,a,b);
endmodule