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Hi3521DV100DMEB_VER_B_PCB Altium Designer版
Hi3521DV100DMEB_VER_B_PCB 海思原厂DEMO PCB板Altium Designer版本
2020-11-12
Hi3521DV100DMEB_VER_B_SCH Altium Designer版本
Hi3521DV100DMEB_VER_B_SCH Altium Designer版本原厂DEMO硬件原理图
2020-11-12
HI3519AV100LPDDR4TB_VER_B_PCB.PcbDoc
海思HI3519AV100LPDDR4TB_VER_B_PCB官方参考设计,转Altium Designer版本
2020-05-08
MT53E256M16D1.pdf
LPDDR4/LPDDR4X SDRAM,MT53E256M16D1, MT53E256M32D2,LPDDR4/LPDDR4X SDRAM
MT53E256M16D1, MT53E256M32D2
Features
This data sheet is for LPDDR4 and LPDDR4X unified
product based on LPDDR4X information. Refer to
LPDDR4 setting section LPDDR4 1.10V VDDQ at the
end of this data sheet.
• Ultra-low-voltage core and I/O power supplies
– VDD1 = 1.70–1.95V; 1.80V nominal
– VDD2 = 1.06–1.17V; 1.10V nominal
– VDDQ = 1.06–1.17V; 1.10V nominal
or Low VDDQ = 0.57–0.65V; 0.60V nominal
• Frequency range
– 1866–10 MHz (data rate range: 3733–20 Mbps/
pin)
• 16n prefetch DDR architecture
• 8 internal banks per channel for concurrent operation
• Single-data-rate CMD/ADR entry
• Bidirectional/differential data strobe per byte lane
• Programmable READ and WRITE latencies (RL/WL)
• Programmable and on-the-fly burst lengths (BL =
16, 32)
• Directed per-bank refresh for concurrent bank operation
and ease of command scheduling
• Up to 8.5 GB/s per die
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh (PASR)
• Selectable output drive strength (DS)
• Clock-stop capability
• RoHS-compliant, “green” packaging
• Programmable VSS (ODT) termination
2020-03-09
MT53B256M32D1NP.pdf
Mobile LPDDR4 SDRAM,MT53B256M32D1, MT53B512M32D2, MT53B1024M32D4,Features
• Ultra-low-voltage core and I/O power supplies
– VDD1 = 1.70–1.95V; 1.8V nominal
– VDD2/VDDQ = 1.06–1.17V; 1.10V nominal
• Frequency range
– 1600–10 MHz (data rate range: 3200–20 Mb/s/
pin)
• 16n prefetch DDR architecture
• 2-channel partitioned architecture for low RD/WR
energy and low average latency
• 8 internal banks per channel for concurrent operation
• Single-data-rate CMD/ADR entry
• Bidirectional/differential data strobe per byte lane
• Programmable READ and WRITE latencies (RL/WL)
• Programmable and on-the-fly burst lengths (BL =
16, 32)
• Directed per-bank refresh for concurrent bank operation
and ease of command scheduling
• Up to 12.8 GB/s per die (2 channels x 6.4 GB/s)
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh (PASR)
• Selectable output drive strength (DS)
• Clock-stop capability
• RoHS-compliant, “green” packaging
• Programmable VSSQ (ODT) termination
2020-02-25
RTL8153B-VB-CG_REALTEK.pdf
INTEGRATED 10/100/1000M ETHERNETCONTROLLER FOR USB 3.0 APPLICATIONS
2020-02-21
IMX291LQR-C-Sony.pdf
IMX291LQR-C Image Sensor MIPI接口 datasheet The IMX291LQR-C is a diagonal 6.46 mm (Type 1/2.8) CMOS active pixel type solid-state image sensor with a
square pixel array and 2.13 M effective pixels. This chip operates with analog 2.9 V, digital 1.2 V, and interface 1.8 V
triple power supply, and has low power consumption. High sensitivity, low dark current and no smear are achieved
through the adoption of R, G and B primary color mosaic filters. This chip features an electronic shutter with variable
charge-integration time.
(Applications: Surveillance cameras, FA cameras, Industrial cameras)
2020-02-21
Altium Library Loader.zip
Altium Library Loader AD封装库下载神器,直接输入元器件型号搜索下载即可,自动生成原理图库,PCB封装库,亲测可用
2019-08-22
RK_SAPPHIRE_SOCBOARD_RK3399_LPDDR3D178P232SD8_V12_20161110_final_lint.PcbDoc
RK3399参考设计PCB文件 Altium Designer版本可以直接打开.
2019-05-16
K3D-MM70-314-310B1-V2_JAE_Proprietary.STEP
MXM3.0 compatible connector, 6.7mm height,314 pos. (310),Soldering (SMT),3D STEP
2019-05-16
程序设计与数据结构(仅供阅览不可印刷)周立功
2017-09-14
source insight 4.0.0086 注册机序列号Patched(20170729)
2017/07/29 更新
1. 安装原版软件:Source Insight Version 4.0.0086
2. 替换原主程序:sourceinsight4.exe
3. 导入授权文件(Import a new license file):si4.pediy.lic
本次更新主要解决了Windows系统用户名含日文或中文等非ANSI字符时,创建“工程/项目”列表或打开“工程/项目”报错的问题。
Patched sourceinsight4.exe:
2017-07-29
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