verilog 系统函数 $display $write $fopen

 

显示函数：

 

$display([ mcd, ] "text", signal, signal, ...);
$write( [ mcd, ] "text", signal, signal, ...);
$strobe( [ mcd, ] "text", signal, signal, ...);
$monitor( [ mcd, ] "text", signal, signal, ...);

%b or %B	Binary format
%d or %D	Decimal format (default)
%h or %H	Hexadecimal format
%o or %O	Octal format
%e or %E	Real in exponential format
%f or %F	Real in decimal format
%g or %G	Real in decimal or exponential format (shortest result)
%c or %C	Character
%s or %S	String
%t or %T	Time format
%m or %M	Hierarchical name
%v or %V	Net signal strength

Example:

$display("The binary value of A is: %b", A);
$write("The register values are: ", Reg1,, Reg2,, Reg3, "\n");

initial begin
  A = 0;
  $display(A);      // displays 0
  $strobe(A);       // displays 1
  A = 1;
end

 

 

文件读取函数：

mcd = $fopen("file_name" [ , type ] );
$fclose(mcd);
$readmemb("file_name", memory_name [ , start_address [ , end_address ]] );
$readmemh("file_name", memory_name [ , start_address [ , end_address ]] );
c = $fgetc(mcd);
ungetc(c, mcd);
i = $fgets(str, mcd);
i = $fscanf(mcd, "text", signal, signal, ...);
i = $sscanf(str, "text", signal, signal, ...);
i = $fread(reg_or_mem, mcd [ , start_address [ , end_address ]] );i = $ftell(mcd);
i = $fseek(mcd, offset, operation);
i = $rewind(mcd);
$fflush( [ mcd ] );
i = $ferror(mcd, str);
$swrite(output_reg, signal, signal, ...));
$sformat(output_reg, text", signal, signal, ...); 

Type	Description
"r" or "rb"	Open for reading
"w" or "wb"	Create for writing
"a" or "ab"	Append
"r+" or "rb+" or "r+b"	Open for update (reading and writing)
"w+" or "wb+" or "w+b"	Create for update
"a+" or "ab+" or "a+b"	Append; open or create for update at end-of-file

Example:

initial begin
  File = $fopen("Result.dat");
  if (!File)
    $display("Could not open \"result.dat\"");
  else begin
    $display(File, "Result is: %4b", A);
    $fclose(File);
  end
end

reg [7:0] Memory [15:0];
initial begin
  $readmemb("Stimulus.txt", Memory);
end