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CPUThermometer 一个方便查看 CPU 温度的工具（WIN10）

This document is the protocol specifications for the Sentech Standard GigE Vision camera.

TCL脚本 提取 WIN10 聚焦目录中的墙纸， 提取出尺寸为 1920x1080 的JPG图片。（只将1080p的图片复制到结果的目录下）

ug901-vivado-synthesis-examples 一些 xilinx 参考代码示例。

6 Gb/s Signal/Data Serial Interface — Electrical

6G-SDI Bit-Serial Interfaces - Overview for the SMPTE ST 2081

6G-SDI 2160-Line and 1080-Line Source Image and Ancillary Data Mapping

12 Gb/s Signal/Data Serial Interface — Electrical

12G-SDI Bit-Serial Interfaces — Overview for the SMPTE ST 2082 Document Suite

2160-line Source Image and Ancillary Data Mapping for 12G-SDI

This application note describes a simple and efficient FPGA configuration method that utilizes a microprocessor to configure an FPGA device from a Serial Peripheral Interface (SPI) flash memory. This method reduces hardware components, board space, and costs. Reference hardware design and firmware are included to illustrate the methodology.

Foobar2000+FooBox+6th+Edition+v6.1.4.01 目前最好用的音频播放器

Tcl_Tk入门经典 , 特别适合于开发硬件，能够极大提高工作效率，目前主流的硬件开发工具都是支持 TCL 脚本。 高效提升代码执行水平

smpte 定义的 uhd-sdi 视频传输格式标准，包含 6G-SDI 和 12G-SDI 协议标准

XILINX ZYNQ 交叉编译器 xilinx-2012.03-79-arm-xilinx-linux-gnueabi.bin

This document describes how to create, test and configure a Linux image with Custom IP UIO Driver using PetaLinux 2014.4 on Ubuntu 14.04 LTS (64-bit). Ubunto 14.04 LTS (64-bit) Guest is running Oracle VM VirtualBox 4.3.20 on a Windows 7 Professional Service pack 1 (64-bit) Host.

This document describes how to build a Processor System (PS) system with custom IP and interrupt support for the Avnet MicroZed development board using Vivado 2014.4 on Ubuntu 14.04 LTS (64-bit). Ubunto 14.04 LTS (64-bit) Guest is running Oracle VM VirtualBox 4.3.20 on a Windows 7 Professional Service pack 1 (64-bit) Host.

EMMC协议 PPT 详细介绍该协议的相关技术特点，方便用户开发

SDI to Video Bridges Quickly bridge SDI inputs and outputs to video and synchronization signals that can then be used with the Xilinx video to/from AXI4-Stream cores The LogiCORE? IP SDI Tx and RX Video Bridge cores are designed to interface the SDI ports of the SMPTE SDI core to the video ports of the AXI4-Stream core. The input of the SDI Rx Video Bridge is an SDI virtual interface that has one to four 10-bit data streams with embedded synchronization. The output is video data with explicit synchronization signals. This core extracts synchronization signals, reformats the video data, and provides clock enables. The input of the SDI TX Video Bridge core is Video data with explicit synchronization signals. The output is an SDI virtual interface with one to four 10-bit data streams and embedded synchronization. Key Features ?Embeds and extracts synchronization signals into and out of the SDI data stream. ?Creates and embeds line numbers into the SDI data stream. ?Generates clock enables for SDI-SDI and 3G-SDI level B modes. ?Supports YCbCr data format at 10-bits per component. ?Supports SD-SDI, HD-SDI, 3G-SDI Level A, and 3G-SDI Level B. ?Re-orders sequential video data to parallel data in 3G Level B and vice versa. ?Supports interlaced and progressive line standards. Embeds and extracts synchronization signals into and out of the SDI data stream.

Quickly bridge SDI inputs and outputs to video and synchronization signals that can then be used with the Xilinx video to/from AXI4-Stream cores

xilinx xdma