TMS320F28335 CAN调试代码

/*
 * hal_canb.c
 *
 *  Created on: 2023年12月18日
 *      Author: 49300
 */
#include <stdint.h>
#include <hal_gpio.h>
#include <hal_timer.h>
#include <hal_canb.h>
#include <app.h>
#include "DSP2833x_Device.h"
#include "DSP2833x_Examples.h"
#include "PeripheralHeaderIncludes.h"

extern unsigned int systemTickMs;

void CANB_GPIO_Init(void)
{
    EALLOW;
    /*GPIO12 CABTXB*/
    GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0;      // 0 = Enable pull-up
    GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2;     // 0=GPIO,  1=Trip Zone,  2=CANTXB,  3=MDRB

    /*GPIO13 CABRXB*/
    GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0;      // 0 = Enable pull-up
    GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2;     // 0=GPIO,  1=Trip Zone,  2=CANRXB,  3=MDXB
    GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3;
    EDIS;
}

void CANB_Reg_Config(void)
{
    /* Create a shadow register structure for the CAN control registers. This is
     needed, since only 32-bit access is allowed to these registers. 16-bit access
     to these registers could potentially corrupt the register contents or return
     false data. This is especially true while writing to/reading from a bit
     (or group of bits) among bits 16 - 31 */

        struct ECAN_REGS ECanbShadow;
        EALLOW;      // EALLOW enables access to protected bits

    /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/

        ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all;
        ECanbShadow.CANTIOC.bit.TXFUNC = 1;
        ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all;

        ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all;
        ECanbShadow.CANRIOC.bit.RXFUNC = 1;
        ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all;

    /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */

        ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
        ECanbShadow.CANMC.bit.SCB = 1;
        ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;

    /* Initialize all bits of 'Master Control Field' to zero */
    // Some bits of MSGCTRL register come up in an unknown state. For proper operation,
    // all bits (including reserved bits) of MSGCTRL must be initialized to zero

        ECanbMboxes.MBOX0.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX1.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX2.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX3.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX4.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX5.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX6.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX7.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX8.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX9.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX10.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX11.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX12.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX13.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX14.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX15.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX16.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX17.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX18.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX19.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX20.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX21.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX22.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX23.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX24.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX25.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX26.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX27.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX28.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX29.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX30.MSGCTRL.all = 0x00000000;
        ECanbMboxes.MBOX31.MSGCTRL.all = 0x00000000;

    // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
    //  as a matter of precaution.

        ECanbRegs.CANTA.all = 0xFFFFFFFF;   /* Clear all TAn bits */
        ECanbRegs.CANRMP.all = 0xFFFFFFFF;  /* Clear all RMPn bits */
        ECanbRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
        ECanbRegs.CANGIF1.all = 0xFFFFFFFF;

    /* Configure bit timing parameters for eCANB*/

        ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
        ECanbShadow.CANMC.bit.CCR = 1 ;            // Set CCR = 1
        ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
        ECanbShadow.CANES.all = ECanbRegs.CANES.all;

        do
        {
            ECanbShadow.CANES.all = ECanbRegs.CANES.all;
        } while(ECanbShadow.CANES.bit.CCE != 1 );       // Wait for CCE bit to be  cleared..


        ECanbShadow.CANBTC.all = 0;

        #if (CPU_FRQ_150MHZ)                       // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
        /* The following block for all 150 MHz SYSCLKOUT - default. Bit rate = 500K */
            ECanbShadow.CANBTC.bit.BRPREG = 9;
            ECanbShadow.CANBTC.bit.TSEG2REG = 2;
            ECanbShadow.CANBTC.bit.TSEG1REG = 10;
        #endif

        ECanbShadow.CANBTC.bit.SAM = 1;
        ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all;

        ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
        ECanbShadow.CANMC.bit.CCR = 0 ;            // Set CCR = 0
        ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;

        ECanbShadow.CANES.all = ECanbRegs.CANES.all;

        do
        {
            ECanbShadow.CANES.all = ECanbRegs.CANES.all;
        } while(ECanbShadow.CANES.bit.CCE != 0 );       // Wait for CCE bit to be  cleared..


    /* Disable all Mailboxes  */
        ECanbRegs.CANME.all = 0;        // Required before writing the MSGIDs
        EDIS;
}

void CANB_Mailbox_Config(void)
{
    struct ECAN_REGS ECanbShadow;
    EALLOW;

    ECanbShadow.CANME.all = ECanbRegs.CANME.all;
    ECanbShadow.CANME.bit.ME1 = 0; // can tx mailbox disable
    ECanbShadow.CANME.bit.ME2 = 0; // can rx mailbox disable
    ECanbRegs.CANME.all = ECanbShadow.CANME.all;

    ECanbShadow.CANMD.all = ECanbRegs.CANMD.all;
    ECanbShadow.CANMD.bit.MD1 = 0;  //0:transmit mode 1:recv mode
    ECanbShadow.CANMD.bit.MD2 = 1;  //0:transmit mode 1:recv mode
    ECanbRegs.CANMD.all = ECanbShadow.CANMD.all;

    ECanbMboxes.MBOX1.MSGCTRL.bit.DLC = 8; //tx data length
    ECanbMboxes.MBOX1.MSGID.bit.STDMSGID = 0x22;//tx id
    ECanbMboxes.MBOX1.MSGID.bit.AME = 0;   //No acceptance mask is used
    ECanbMboxes.MBOX1.MSGID.bit.IDE = 0;   //standard identifier (11 bits)

    ECanbMboxes.MBOX1.MSGID.bit.IDE = 0;

    ECanbMboxes.MBOX2.MSGCTRL.bit.DLC = 8; //rx data length
    ECanbMboxes.MBOX2.MSGID.bit.STDMSGID = 0x55;//rx id
    ECanbMboxes.MBOX2.MSGID.bit.AME = 0;   //filter mask is used
    ECanbMboxes.MBOX2.MSGID.bit.IDE = 0;   //standard identifier (11 bits)
    ECanaLAMRegs.LAM2.all = 0x01;
    ECanbRegs.CANRMP.all   = 0xFFFFFFFF;

    ECanbShadow.CANME.all = ECanbRegs.CANME.all;
    ECanbShadow.CANME.bit.ME1 = 1; // can mailbox enable
    ECanbShadow.CANME.bit.ME2 = 1; // can mailbox enable
    ECanbRegs.CANME.all = ECanbShadow.CANME.all;

    EDIS;
}


void CANB_Init(void)
{
    CANB_GPIO_Init();
    CANB_Reg_Config();
    CANB_Mailbox_Config();
}

int CAN_Send_Test(void)//发送一帧数据
{
    struct ECAN_REGS ECanbShadow;

//    uart_printf("%s %d\r\n",__func__,__LINE__);
    EALLOW;
    /* Write to DLC field in Master Control reg */

    ECanbMboxes.MBOX1.MSGCTRL.bit.DLC = 8;

    /* Write to the mailbox RAM field */

    ECanbMboxes.MBOX1.MDL.all = 0x11223344;
    ECanbMboxes.MBOX1.MDH.all = 0x55667788;

    ECanbShadow.CANTRS.all = 0;
    ECanbShadow.CANTRS.bit.TRS1 = 1;             // start transmit
    ECanbRegs.CANTRS.all = ECanbShadow.CANTRS.all;

    do
    {
        ECanbShadow.CANTA.all = ECanbRegs.CANTA.all;
    } while(ECanbShadow.CANTA.bit.TA1 == 0); //tx ack


    ECanbShadow.CANTA.all = 0;
    ECanbShadow.CANTA.bit.TA1 = 1;               // Clear TA5
    ECanbRegs.CANTA.all = ECanbShadow.CANTA.all;
    EDIS;
    return 0;
}

int CAN_Send(unsigned char * msg)//发送一帧数据
{
    struct ECAN_REGS ECanbShadow;

//    uart_printf("%s %d\r\n",__func__,__LINE__);
    EALLOW;
    /* Write to DLC field in Master Control reg */

    ECanbMboxes.MBOX1.MSGCTRL.bit.DLC = 8;

    /* Write to the mailbox RAM field */
    ECanbMboxes.MBOX1.MDL.byte.BYTE0 = msg[0];
    ECanbMboxes.MBOX1.MDL.byte.BYTE1 = msg[1];
    ECanbMboxes.MBOX1.MDL.byte.BYTE2 = msg[2];
    ECanbMboxes.MBOX1.MDL.byte.BYTE3 = msg[3];

    ECanbMboxes.MBOX1.MDH.byte.BYTE4 = msg[4];
    ECanbMboxes.MBOX1.MDH.byte.BYTE5 = msg[5];
    ECanbMboxes.MBOX1.MDH.byte.BYTE6 = msg[6];
    ECanbMboxes.MBOX1.MDH.byte.BYTE7 = msg[7];


//    ECanbMboxes.MBOX1.MDL.all = 0x11223344;
//    ECanbMboxes.MBOX1.MDH.all = 0x55667788;

    ECanbShadow.CANTRS.all = 0;
    ECanbShadow.CANTRS.bit.TRS1 = 1;             // start transmit
    ECanbRegs.CANTRS.all = ECanbShadow.CANTRS.all;

    do
    {
        ECanbShadow.CANTA.all = ECanbRegs.CANTA.all;
    } while(ECanbShadow.CANTA.bit.TA1 == 0); //tx ack


    ECanbShadow.CANTA.all = 0;
    ECanbShadow.CANTA.bit.TA1 = 1;               // Clear TA5
    ECanbRegs.CANTA.all = ECanbShadow.CANTA.all;
    EDIS;
    return 0;
}

void CANB_Recv(void)
{
    struct ECAN_REGS ECanbShadow;
    unsigned char recvBuff[8];
    unsigned char recvID;
    unsigned long int MDL,MDH;

    ECanbShadow.CANRMP.all = ECanbRegs.CANRMP.all;

    if(ECanbShadow.CANRMP.bit.RMP2 == 1)//message received when RMP set
    {
        MDL = ECanbMboxes.MBOX2.MDL.all; // = 0x (n is the MBX number)
        MDH = ECanbMboxes.MBOX2.MDH.all; // = 0x (a constant)
        recvID = ECanbMboxes.MBOX2.MSGID.all;// = 0x (n is the MBX number)

        recvBuff[3] = MDL & 0xff;
        recvBuff[2] = (MDL >> 8) & 0xff;
        recvBuff[1] = (MDL >> 16) & 0xff;
        recvBuff[0] = (MDL >> 24) & 0xff;

        recvBuff[7] = MDH & 0xff;
        recvBuff[6] = (MDH >> 8) & 0xff;
        recvBuff[5] = (MDH >> 16) & 0xff;
        recvBuff[4] = (MDH >> 24) & 0xff;

        ECanbShadow.CANRMP.bit.RMP2 = 1;//recv message flag set 1 to clear
        ECanbRegs.CANRMP.all=ECanbShadow.CANRMP.all;

        uart_printf("id=%d ",recvID);
        uart_printf("%d %d %d %d ", recvBuff[0] ,recvBuff[1] ,recvBuff[2] ,recvBuff[3] );
        uart_printf("%d %d %d %d\r\n", recvBuff[4] ,recvBuff[5] ,recvBuff[6] ,recvBuff[7]);
    }
}

void CANB_Test(void)
{
    static unsigned int canTickMs = 0;
    unsigned char txbuff[8];
    int i = 0;

    for(i = 0; i < 8; i++)
    {
        txbuff[i] = 0x11 + i;
    }


    int timerflag = 0;

    if(systemTickMs > canTickMs)
    {
      if((systemTickMs - canTickMs) > 1000)
      {
          canTickMs  = systemTickMs;
          timerflag = 1;
      }
    }
    else if (systemTickMs < canTickMs)
    {
      if(((0xFFFF - canTickMs) + systemTickMs) > 1000)
      {
          canTickMs  = systemTickMs;
          timerflag = 1;
      }
    }

    if(timerflag)
    {
        GpioDataRegs.GPCTOGGLE.bit.GPIO65 = 1;
//        CAN_Send_Test();
        CAN_Send(txbuff);
    }
}