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深入浅出玩转fpga.pdf
深入浅出玩转fpga
第一部分 基础普及
笔记1 初识FPGA
笔记2 应用领域
笔记3 开发流程
第二部分 设计技巧
笔记4基本语法
笔记5 漫谈状态机设计
笔记6 复位设计
笔记7 FPGA重要设计思想及工程应用
笔记8 基于FPGA的跨时钟域信号处理
笔记9 经验点滴
第三部分 仿真测试
笔记10 简单的Testbench设计
笔记11 Testbench书写技巧
笔记12 测试用例设计
第四部分 时序分析
笔记13 时序分析基础
笔记14 基于ISE的时序约束
笔记15 基于TimeQuest的时序分析
第五部分 基础实验
笔记16 基于EPM240的入门实验
笔记17 基于EP1C3的进阶实验
第六部分 项目应用
笔记18 DIY逻辑分析仪
笔记19 DIY数码相框
第七部分 网络杂文
笔记20 Xilinx网站资源导航
笔记21 苦练基本功
笔记22 永远忠于年轻时的梦想
参考文献
Writing Testbenches using systemverilog.pdf
verilog编写testbench国外经典教材
Verification is too often approached in an ad hoc fashion. Visually inspecting simulation results is no longer feasible and the directed test-case methodology is reaching its limit. Moore's Law demands a productivity revolution in functional verification methodology. Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source management tools, from specification to functional coverage, from I's and O's to high-level abstractions, from interfaces to bus-functional models, from transactions to self-checking testbenches, from directed testcases to constrained random generators, from behavioral models to regression suites, this book covers it all. Writing Testbenches Using SystemVerilog presents many of the functional verification features that were added to the Verilog language as part of SystemVerilog. Interfaces, virtual modports, classes, program blocks, clocking blocks and others SystemVerilog features are introduced within a coherent verification methodology and usage model. Writing Testbenches Using SystemVerilog introduces the reader to all elements of a modern, scalable verification methodology. It is an introduction and prelude to the verification methodology detailed in the Verification Methodology Manual for SystemVerilog. It is a SystemVerilog version of the author's bestselling book Writing Testbenches: Functional Verification of HDL Models.