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简单verilog testbench
简单verilog testbench
`timescale 1ns/1ns
module tb_jet_ctrl_top();
parameter U_DLY = 1;
integer i;
reg rst_n;
reg clk;
reg [ 7:0] cpu_dat;
reg [11:8] cpu_addr;
reg cpu_cs;
reg cpu_wr_n;
reg prt_trig_n;
initial begin
rst_n = 1'd0;
#100;
rst_n = 1'd1;
end
initial begin
clk = 1'd0;
2014-01-25
verilog FSM 范例
verilog FSM 范例
//FSM
always @(posedge clk or negedge rst_n)begin
if(rst_n == 1'd0)begin
sta_curr <= S_IDLE;
end
else begin
sta_curr <=#U_DLY sta_next;
end
end
always @(*)begin
case(sta_curr)
S_IDLE:begin
if(s_idle_jump==1'd1)
sta_next = S_PRE_DLY;
else
sta_next = S_IDLE;
end
S_PRE_DLY:begin
if(s_pre_dly_jump==1'd1)
sta_next = S_WAIT_LE;
else
sta_next = S_PRE_DLY;
end
2014-01-25
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