u013566585的博客

讲一些在Verilog和SystemVerilog coding中容易发生的一些错误，以及如何避免。 paper及PPT发表在 SNUG Boston 2006 上。Standard Gotchas-in the Verilog and SystemVerilog Standards That Every Engineer Should Know 。 The Verilog and SystemVerilog standards define hundreds of subtle rules on how software tools should interpret design and testbench code. These subtle rules are documented in the IEEE Verilog and SystemVerilog Language Reference Manuals...all 1,500 plus pages! The goal of this paper is to reveal many of the mysteries of Verilog and SystemVerilog, and help engineers understand many of the important underlying rules of the Verilog and SystemVerilog languages. Dozens of gotchas in the standards are explained, along with tips on how to avoid these gotchas.